JP3340786B2 - Power transistor overcurrent protection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power transistor, and more particularly, to a current-driven transistor such as an IGBT or a MOSFET, in which an overcurrent caused by a load short-circuit or the like is limited at a high speed and cut off and protected in a safe operation area. The present invention relates to an overcurrent protection circuit for a power transistor which enables the following.

[0002]

2. Description of the Related Art An IGBT (insulated gate bipolar mode transistor) is rapidly expanding its application field because of its low on-voltage, low driving power in a MOS gate structure, and relatively high-speed switching.

[0003] The characteristics of the ON voltage and the switching speed are in a trade-off relationship, and research is being conducted day and night to improve the trade-off and to obtain a device with higher performance. Characteristic C in FIG.
Is the third generation of IGB predicted from these studies.
The on-voltage characteristic of T is shown in comparison with the on-voltage characteristic A of the first generation IGBT. Current IGBTs are shown in characteristic B in the second generation. The collector current I _C is shown as a percentage with the rated current of the IGBT as 100.

As is apparent from these characteristics, when the collector-emitter voltage V _CE rises due to a load short circuit or the like, a collector current I _C several times the rated current flows, and the first generation IG
Overcurrent flows 6 to 8 times in the BT and 10 to 12 times in the second generation IGBT.

[0005] In the IGBTs of the third and subsequent generations, which are currently under study, a pattern of the order of μm of a DRAM class and other improvements are applied, so that an overcurrent of more than ten times as shown by the characteristic C flows.

[0006] When such a large overcurrent occurs, if the current is cut off at a high speed, the surge voltage becomes excessive, making it difficult to safely protect the device.

Hereinafter, protection of a conventional IGBT when a load is short-circuited will be described. FIG. 4 shows a general main circuit configuration of an inverter using an IGBT. This inverter is
The motor 3 is driven by converting the DC voltage of the DC voltage source 1 into an AC voltage by a bridge type converter composed of IGBTs 21 to 26.

In such a device, when a short circuit occurs between terminals on the load (motor) side, a short circuit current flows through the positive and negative IGBTs. Similarly, when an ON signal (a signal due to noise or malfunction) is simultaneously input to the positive and negative IGBTs of the same arm, a short-circuit current flows.

The short-circuit withstand capability of an IGBT capable of withstanding such a short-circuit state is 80% of the element rated voltage in the current IGBT.
10 to 20 μs at a voltage of 7.5 to 10 μs
Short circuit protection that detects overcurrent within the current limit and shuts off the current is performed.

FIG. 7B shows the collector-emitter voltage V
FIG. 7A is a characteristic diagram of the short-circuit withstand capability showing the relationship between the collector current I _C flowing at the time of short-circuit under a constant _CR and the withstand time (t ₁ ). As is apparent from this characteristic, I _C and t ₁ have a substantially constant power relationship. When the collector current I _C increases due to a load short circuit or the like, the withstand time t ₁ becomes shorter, and a high-speed protection operation is required.

Therefore, various methods have been proposed to detect a load short circuit, reduce the gate voltage of the IGBT, limit the short-circuit current by utilizing the transistor function of the IGBT, and increase the apparent short-circuit withstand time.

FIG. 8 is also a kind of this one, which was announced at the 197th Annual Meeting of the Institute of Electrical Engineers of Japan in 470. FIG.
A current sense IGBT 4b is provided in addition to the GBT 4a, and when the current exceeds a set current, the NLU circuit 50 short-circuits the gate (G) and the emitter (E) of the IGBT to lower the gate voltage and suppress the short-circuit current.

In the circuit of FIG. 9A showing an example of the NLU circuit, the emitter current of the current sense IGBT 4b is converted into a voltage by the resistor 52, and when the current exceeds the gate threshold voltage of the MOSFET 54 via the resistor 53, the drain of the MOSFET is drained. A current flows to lower the gate voltage of the IGBT 4.

The circuit shown in FIG.
Is replaced with a bipolar transistor 55. When such a circuit is configured, the gate voltage of the IGBT is reduced at the time of an overcurrent, and the ON resistance of the IGBT is increased.
As shown in FIG. 8C, the short-circuit current can be limited, and the short-circuit withstand time can be apparently increased as shown in FIG.

[0015]

The conventional method of FIG. 8 increases the short-circuit tolerance of the IGBT module, but requires a separate circuit for detecting a short-circuit accident and turning off the signal driving the IGBT bridge.

In this method, the short-circuit current is rapidly limited to about 200%, so that (a) it is difficult to detect a short-circuit accident by detecting an overcurrent. (B) complex another short-circuit fault detection circuit must be added to the circuit to turn off the driving signals by such circuits, such as detection that the V _CE of the IGBT because this remains high added-on signal Becomes

(C) In the circuit of FIG.
Even if the drain current of the FET 54 in FIG. 9A is the same depending on the size of g51, the gate voltage value is different, so that there is a disadvantage that the current limit value differs as shown in FIG. 6 depending on the size of Rg.

The change in the limit value current can be reduced by increasing the drain current gain with respect to the current detection value shown in FIG. 9A.
The SFET 54 is not an analog operation but a switching operation, the gate of the IGBT 4 drops to near zero, and the current of the IGBT is turned on and off to oscillate, so that there is a limit. Therefore, the characteristics are as shown in FIG. If Rg is reduced in order to make the switching of the IGBT faster, the short-circuit current limit value increases, and the short-circuit withstand time becomes short.

(D) Next, there is a problem when IGBT modules are connected in parallel. In the method shown in FIG. 8, since the current limiting function is housed inside each module, the operation level of each module is different. Therefore, if the current limiting function of one module malfunctions, the on-resistance of this module increases, the current moves to the adjacent module, and the current limiting function of this module operates. By repeating this, there is a risk that a kind of oscillation state occurs and the IGBT deteriorates.

[0020] (e) then become a problem NLU speed during cutoff of the peak value of the current in there scheme is limited but the current is faster floating inductance l ₀ surge voltage (-l ₀ · due 8 (dic / dt), there is a risk that the element may be deteriorated beyond the safe operation of the IGBT.

FIG. 7 shows an example of the safe operation area of the IGBT.
It is shown in (c). Surge voltage V higher current I _C is increased
_CEP needs to be lowered. In particular, when the capacity of the converter increases, the fault current also increases, but since the stray inductance cannot be reduced due to its structure, the surge voltage tends to increase accordingly.

Therefore, the only way to reduce the surge voltage is to reduce the current change rate dic / dt. (F) Eventually, the current limited to 250% to 500% is cut off by turning off the drive signal. Surge voltage generated at this time _{-L 0 · di / dt (L} 0 is the leakage inductance, di / dt is the current change rate) determined by and passes through the reverse bias safe operating area outside of the transistor by the surge voltage transistor permanent to degrade. (IG
The safe operation area of the BT drops to about 80% of the rated voltage when the 200% current is cut off.) Especially when the capacity of the converter increases, L ₀ also tends to increase,
Moreover, since the current i is proportional to the capacity, the surge voltage increases remarkably. For this reason, the snubber circuit (surge absorbing circuit) may occupy a larger volume and cost than the main element transistor.

According to the present invention, under the above-mentioned technical background, an overcurrent of a transistor having a small on-state voltage and a large short-circuit current is detected, this current is limited at a high speed, and then the fault current is softly cut off. An object of the present invention is to provide a highly reliable power transistor protection circuit by suppressing a generated surge voltage.

[0024]

To achieve the above object, the present invention provides a power transistor for supplying a current to a load by a switching operation, and a current signal having a voltage corresponding to the current flowing through the power transistor. A current control loop that suppresses a current flowing through the power transistor by lowering a drive signal level of the power transistor by bypassing a current proportional to a portion where the current signal exceeds a predetermined value from a gate circuit that drives the power transistor. A circuit that closes and self-holds when the bypass current continues for a predetermined time and gradually shunts the bypass current; and gradually increases the shunt current to switch from the current control loop to an open loop to drive signal level. Lower.

Further, when the bypass current flows, the state of the drive signal of the power transistor is maintained, and when the bypass current continues for a predetermined time, the drive signal is turned off. Further, the self-holding circuit, which is closed when the bypass current continues for a predetermined time, is reset by turning off the drive signal.

[0026]

When an overcurrent flows through the power transistor and exceeds a predetermined value, a bypass current proportional to the current flows from the gate circuit to lower the gate voltage. When the gate voltage decreases, the conduction resistance of the power transistor increases, and a current control loop that suppresses the overcurrent functions, and the overcurrent is maintained at about a predetermined value. When the bypass current flows, the drive signal of the power transistor is kept in the ON state, and the OFF operation by the drive signal is not performed. When the bypass current flows continuously for a predetermined time, the predetermined circuit is closed and self-holds, and the bypass current is gradually divided into the predetermined circuit, and is added to the control signal of the current control loop and flows. When the shunt current gradually increases and exceeds the bypass current by the current control loop, the operation is switched to an open loop, the gate voltage further decreases gradually, and the current flowing through the power transistor is cut off gently. When the bypass current continues for a certain period of time (including the time until the current of the power transistor becomes zero), the drive signal is returned to the off state, the self-hold state is released, and the state returns to the initial state.

[0027]

FIG. 1 shows an embodiment of the present invention. In FIG. 1, the IGBT 4 is usually connected to the DC power supply 1 via a load, but the case where the load impedance is zero is shown in order to protect the load when the load is short-circuited. IGBT4
A part of the current on the emitter side is converted into a voltage by the resistor 11 to form an emitter follower circuit including the transistor 12 and the resistor 13.

The gate drive circuit of the IGBT 4 is a DC power supply.
Using the drive power supplies 14 and 15 as the drive power supply, the drive signal is insulated by the photocoupler 16 and the drive signal amplified by the amplifier 17 drives the bases of the transistors 32 and 33 via the resistor 18 to obtain positive and negative gate drive voltages. The gate of the IGBT 4 is driven via the gate resistor 34. The emitter of the IGBT 4 is connected to the DC power supply 14
Since the gate drive voltage is at the potential of the 15 series connection points, the gate drive voltage becomes positive when the transistor 32 is turned on, and becomes negative when the transistor 33 is turned on.

The resistor 18 and the light emitting diode 1 of the photocoupler
9. Connect to the collector side of transistor 12 through diode 20. The cathode side of the diode 20 is connected to the base of the transistor 23 via the resistor 21, and the resistor 22 is connected between the emitter and the base of the transistor. Transistor 23
, The capacitor 25 is charged via the resistor 24. The connection point between the resistor 24 and the capacitor 25 is connected to the base of the transistor 26, and the emitter of the transistor 26 is connected via the resistor 27 to the other end of the capacitor 25 and the series connection point between the DC power supplies 14 and 15. The collector of transistor 26 is a diode
Connect to 20 cathodes. Diode 28 is capacitor 25
And in parallel with each other so that an excessive reverse voltage is not applied to the transistor 26. The base of the transistor 26 is connected to the bases of the transistors 32 and 33 via the resistor 29 and the diode 30. Also, the resistor 31 is connected to the base of the transistor 26.
To the negative side of the DC power supply 15

When a current flows through the light emitting diode 19 of the photocoupler, the light receiving transistor 35 and the resistor 36 of the photocoupler
Are connected in series, and the signal is detected by the failure detection circuit 37,
The PWM signal (pulse width modulation signal) is held via a holding circuit, and is input to the photocoupler 16 via a cutoff circuit 39. The output V37 of the failure detection circuit 37 is connected via the timer circuit 40 to operate the cutoff circuit 39.

The operation of this embodiment having the above configuration will be described with reference to FIG. When the PWM signal is set to “1” at time t ₁ to drive the photocoupler 16 with the voltage V39, the amplifier
And the transistor 33 is turned off via the 17, the transistor 32 is turned on, the gate drive voltage V _G is switched positive switching from a negative.

When a positive voltage is applied to the gate of IGBT 4, I
The GBT turns on. In a state where the load is shorted, the collector current I _C of the DC power source 1 IGBT is applied between the collector and the emitter of the IGBT4 is lowered turned-internal resistance IGBT rapidly in inclination limited by stray inductance L ₀ of the circuit Stand up. A part of this current is detected by the resistor 11, and a current I ₁ proportional to the increase of I _C flows into the collector of the transistor 12 from the point where the detected voltage exceeds the threshold voltage between the base and the emitter of the transistor 12. . The current I ₁ is resistor 18, the photocoupler 19, the circuit voltage drop of the flow resistor 18 is increased to the gate drive voltage V _G of the diode 20 begins to decrease.

On the other hand part of the current I ₁ is resistor 22, the sink also partial circuit of the resistor 21, the transistor 23 through the turned on resistor 24 and outputs a voltage V23 at time t ₃ to start charging the capacitor 25 . The charging voltage V _C rises from negative to positive, and after time t _4, which exceeds the threshold voltage of the base and emitter of the transistor 26, the collector current I ₂ of the transistor 26 is increased by the emitter follower connection between the transistor 26 and the resistor 27. A current proportional to the portion above the threshold voltage of _C will flow. Further, the transistor 23 flows through the I ₂ be I ₁ Since the self-holding reaches zero to maintain this state.

During the period from time t _{2 to} t ₄ , I _C of the IGBT ₄ is used.
When the value exceeds a certain value, I ₁ is supplied to lower the gate voltage of the IGBT, increase the ON resistance of the IGBT, and reduce the I _C to control the short-circuit current to be almost constant.

Next, during the period from time t _{4 to} time t ₆ , the gradually increasing I ₂ is input as a disturbance, and the increased I ₂ decreases I ₁ to balance, and at time t ₆ , I ₁
Becomes zero. Period of t ₄ ~t ₆ is a period of overlap and a signal to reduce the I _C lowered forcibly gate voltage and I _C constant current control, since the I _C constant control loop is operating I _C Is only slightly reduced.

[0036] Then later when I ₁ becomes zero at time t _6, the voltage drop across the resistor 18 increases V _G is gradually with increasing I ₂ (much earlier than between t ₄ ~t ₆₎
Reduced so accordingly I _C is also completely blocked at time t ₇ to the relatively soft it is possible to reduce the V _CE between the surge voltage of the IGBT. Thus an overcurrent state continues beyond the time t ₄ IGBT is reliably shut off a complete operating region.

When the overcurrent state is eliminated before the time t ₄ is reached and I ₁ becomes zero, the transistor 23 is turned off and the capacitor voltage V _C is discharged by the resistor 31. This is to prevent the IGBT from being turned off by self-holding due to noise or short-time overcurrent such as diode recovery current of the opposite phase at the time of bridge connection.

Next, although the PWM signal is turned off at time t ₅ , I ₁ + I ₂ is detected by the photocoupler 19, and the failure detection circuit 37 and the holding circuit 38 of the photocoupler 35 detect the I ₁ + I ₂ via the photocoupler 35. The signal V39 is held.

The timer circuit 40, IGBT 4 of the current I _C is V _G is off the driving signal V39 through the cutoff circuit 39 at time t _8, which is delayed from the time t ₇ to be cut off in a soft
Is quickly turned to a negative voltage, and diode 30, resistor 29
To reverse bias the capacitor 25. As a result, the current of the photocoupler 19 becomes zero, and the failure signal V37 is reset.

According to this embodiment, the short-circuit current can be reduced to 1/4 to 1/5 by forming a constant current control loop of the IGBT.
, The safe operation time at the time of short circuit can be extended. Smooth switching from the constant current control loop to the forced turn-off loop is performed, and thereafter, the gate voltage is gradually lowered to lower the current change rate of the IGBT, thereby lowering the surge voltage and ensuring reliability within the safe operation area of the IGBT. The current can be cut off with good efficiency.

While the overcurrent is flowing, the gate drive signal is held so that the fault current is not cut off at high speed. This is particularly effective in preventing a surge voltage from increasing because the current value increases without reducing the stray inductance when the capacity of the converter increases.

[0042]

[0043]

[0044]

[0045]

As described above, according to the present invention, when the current flowing through the power transistor is equal to or higher than a predetermined value, an automatic control loop for lowering the gate voltage is provided to limit the power transistor current. When a predetermined time has passed, a circuit for detecting and holding this and gradually reducing the gate voltage is provided to cut off the current softly. A power transistor that holds a gate drive signal during this series of operations, extends the short-circuit withstand time of the transistor, and simultaneously shuts down the current softly while reducing the surge voltage. Can be provided.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.

FIG. 2 is a view for explaining the operation of FIG. 1;

FIG. 3 shows a second embodiment of the present invention.

FIG. 4 is a general main circuit diagram of an inverter.

FIG. 5 is a characteristic diagram of a power transistor.

FIG. 6 is a characteristic diagram showing a problem of the conventional device.

FIG. 7 is a diagram for explaining the overcurrent withstand capability of a power transistor.

FIG. 8 is an explanatory view of a conventional device.

FIG. 9 is a detailed description of a part of FIG. 8;

[Explanation of symbols]

1 DC power supply 2 Bridge converter 3 Motor 4
IGBT, 11, 13 ... resistor, 12 ... transistor, 14, 15 ...
DC power supply, 16 photocoupler, 17 amplifier, 18, 21, 2
2, 24, 27 ... resistance, 19, 35 ... photocoupler, 20, 28, 30
... diodes, 23, 26, 32, 33 ... transistors, 25 ... capacitors, 29, 31, 34, 36 ... resistors, 37 ... fault detection circuits,
38: signal holding circuit, 39: signal blocking circuit, 40: timer circuit, 41: amplifier, 42: time delay, 43: holding circuit,
44: Incremental circuit, 45: Reset circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Chihiro Okado 2--24-1, Harumi-cho, Fuchu-shi, Tokyo Toshiba FA System Engineering Co., Ltd. (56) References JP-A-5-227738 (JP, A) JP-A-6-276073 (JP, A)

Claims (3)

(57) [Claims] 1. A power transistor for supplying a current to a load by a switching operation, and a current signal having a voltage corresponding to a current flowing through the power transistor is obtained, and a bypass current proportional to a portion where the current signal exceeds a predetermined value is obtained. A current control loop is provided that bypasses a gate circuit that drives the power transistor and reduces the drive signal level of the power transistor to suppress the current flowing through the power transistor. When the bypass current continues for a predetermined time, the current control loop is closed and self-held. gradually shunt circuit for shunting the bypass current as well as provided, flows in the shunt circuit
An overcurrent protection circuit for a power transistor, wherein a current is gradually increased to switch from the current control loop to an open loop to lower a drive signal level. 2. The overcurrent protection circuit for a power transistor according to claim 1, wherein a state of a drive signal of said power transistor is maintained when said bypass current flows, and said drive is performed when said bypass current continues for a predetermined time. An overcurrent protection circuit for a power transistor, comprising a circuit for turning off a signal. 3. The power transistor overcurrent protection circuit according to claim 2, wherein a self-holding circuit that is closed when said bypass current continues for a predetermined time is reset by an off state of said drive signal. Overcurrent protection circuit.