JP3724255B2 - Gate drive circuit for voltage driven semiconductor device - Google Patents
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Description
【０００１】
【発明の属する技術分野】
この発明は、電力変換装置における電圧駆動型半導体素子のゲート駆動回路、特に電力変換回路を高電圧化するために各アームに電圧駆動型半導体素子を直列接続して構成された電力変換装置における、電圧駆動型半導体素子のゲート駆動回路に関する。
【０００２】
【従来の技術】
図８に、電力変換装置で高電圧化を図るために、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）を各アームに直列接続した場合の従来例で、ＩＧＢＴを直列接続したインバータ１相分の回路を示す。
【０００３】
図示のように、この回路はＩＧＢＴＱ１，Ｑ２（上アーム）とＱ３，Ｑ４（上アーム）、直流電源Ｅｄ、スナバコンデンサＣｓ１，Ｃｓ２、スナバダイオードＤｓ１，Ｄｓ２、スナバ抵抗Ｒｓ１，Ｒｓ２、および各ＩＧＢＴ対応の充放電スナバ回路（ＲＣＤスナバ回路）などから構成される。
【０００４】
ＧＤＵ１〜ＧＤＵ４はＱ１〜Ｑ４のゲート駆動回路で、具体的には例えば図９に示すように、ＩＧＢＴをオン，オフさせるためのトランジスタＴＲ１，ＴＲ２およびインターフェイス回路ＩＦなどから構成される。
【０００５】
図１０に図８，９の動作波形図を示す。
図１０はＱ１がターンオフしてから、時間Δｔ時間だけ遅れてＱ２がターンオフ動作を開始した場合を示している。すなわち、ＩＧＢＴを直列接続して運転する場合、図１０に示すように、素子特性のばらつき等により、ＩＧＢＴのターンオフタイミングに違いが生じると、各ＩＧＢＴの電圧分担にアンバランスが発生する。これは、Ｑ１が早くオフしてしまうと、Ｑ２はオンしているために、Ｑ１だけに電圧が印加されてしまうためである。このようなわけで電圧アンバランスが発生するが、その対策として、各ＩＧＢＴ対応に充放電スナバ回路（図８ではＲＣＤスナバ回路）を付加することによって、Ｑ１（先にオフしたＩＧＢＴ）の電圧変化率（ｄｖ／ｄｔ）を低減させ、Ｑ２（遅れてオフするＩＧＢＴ）がオフするまでの期間（Δｔ）にＱ１に印加される電圧を抑制する。
【０００６】
【発明が解決しようとする課題】
ＩＧＢＴを直列接続して用いる場合、上述のように、各ＩＧＢＴに充放電スナバ回路を付加することにより、ターンオフタイミングがずれた場合の電圧アンバランスによる過電圧印加やそれによる素子破壊を防ぐことができるが、許容し得る時間差を増加させようとすると、付加するスナバのコンデンサ容量を大きくしなければならず、そうすると発生損失が増大するために抵抗Ｒの形状が大きくなり、装置自体も大きくなるなどの問題がある。
したがって、この発明の課題はスナバ回路のコンデンサ容量を大きくすることなく、ＩＧＢＴの高速な保護と再オン時の損失低減を図ることにある。
【０００７】
【課題を解決するための手段】
このような課題を解決するために、請求項１の発明では、各アームに電圧駆動型半導体素子を直列接続してなる電力変換装置に対し、その電圧駆動型半導体素子のスイッチングを制御する制御装置と、この制御装置からの信号に基づき前記各電圧駆動型半導体素子をオン，オフ駆動する駆動回路と、前記電圧駆動型半導体素子に印加される電圧を検出し過電圧かどうかを判断する過電圧判別回路と、前記電圧駆動型半導体素子のターンオフ時に再び電圧駆動型半導体素子をオンさせる再オン回路とを設け、
前記各直列接続された電圧駆動型半導体素子のターンオフタイミングの差により、各電圧駆動型半導体素子の印加電圧にアンバランスが発生したときは、過電圧を検出し、過電圧が印加された電圧駆動型半導体素子を再オンさせることにより、電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止するようにしている。
【０００８】
上記請求項１の発明においては、再オン時のゲート電圧を、前記電圧駆動型半導体素子のしきい値付近の値の電圧レベルに設定することにより、再オン時の発生損失を低減することができ（請求項２の発明）、または、前記各電圧駆動型半導体素子のターンオフ時のゲート電圧を、しきい値電圧と逆バイアス電圧との間の任意の電圧に一定時間クランプするクランプ回路を付加し、再オンまでの時間を高速化することができる（請求項３の発明）。
【０００９】
また請求項４の発明では、各アームに電圧駆動型半導体素子を直列接続してなる電力変換装置に対し、その電圧駆動型半導体素子のスイッチングを制御する制御装置と、この制御装置からのオン，オフ信号に基づき前記各電圧駆動型半導体素子をオン，オフ駆動する駆動回路と、前記電圧駆動型半導体素子に印加される電圧を検出し過電圧かどうかを判断する過電圧判別回路と、前記電圧駆動型半導体素子のターンオフ時に再び電圧駆動型半導体素子を活性領域内でオンさせる再オン回路と、この再オン回路の動作を停止させる再オン停止回路と、電圧駆動型半導体素子のゲート電圧を放電させるリセット回路と、前記制御装置からのオン信号による電圧駆動型半導体素子のオン動作を一定時間遅らせるタイマー回路とを設け、
前記制御装置からオフ信号が発せられたときに前記各直列接続された電圧駆動型半導体素子のターンオフタイミングの差により、各電圧駆動型半導体素子の印加電圧にアンバランスが発生したときは、過電圧を検出し、過電圧が印加された電圧駆動型半導体素子を活性領域内で再オンさせて、該電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止している期間中に
前記制御装置からオン信号が発せられたときには、前記再オン停止回路とリセット回路とを同時に動作させて前記電圧駆動型半導体素子のゲート電圧を放電させた後に、前記電圧駆動型半導体素子をオン動作を開始させることにより、前記各直列接続された電圧駆動型半導体素子のターンオンタイミングの差による各電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止するようにしている。
【００１０】
さらに請求項５の発明では、各アームに電圧駆動型半導体素子を直列接続してなる電力変換装置に対し、その電圧駆動型半導体素子のスイッチングを制御する制御装置と、この制御装置からのオン，オフ信号に基づき前記各電圧駆動型半導体素子をオン，オフ駆動する駆動回路と、前記電圧駆動型半導体素子に印加される電圧を検出し過電圧かどうかを判断する過電圧判別回路と、前記電圧駆動型半導体素子のターンオフ時に再び電圧駆動型半導体素子を活性領域内でオンさせる再オン回路と、この再オン回路の動作を監視する再オン動作監視回路と、前記再オン回路が動作したときには次のターンオフタイミングを所定の時間遅らせるタイミング調整回路とを設け、
前記制御装置からオフ信号が発せられたときに前記各直列接続された電圧駆動型半導体素子のターンオフタイミングの差により、各電圧駆動型半導体素子の印加電圧にアンバランスが発生したときは、過電圧を検出し、過電圧が印加された電圧駆動型半導体素子を活性領域内で再オンさせ、この再オン動作後、該制御装置から次のオフ信号が発せられたときには、このオフ信号にもとづくターンオフタイミングを所定の時間遅らせることにより、前記各直列接続された電圧駆動型半導体素子それぞれの電圧分担を均一化させて、各電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止するようにしている。
【００１１】
【発明の実施の形態】
図１はこの発明の第１の実施の形態を示す構成図で、図８と同じく上，下アームにＩＧＢＴを２直列接続した例である。すなわち、外見上は各ＩＧＢＴのＲＣＤスナバ回路がＲＣスナバ回路になった程度であるが、ゲート駆動装置ＧＤＵが図２に示すように、図９に示すゲート駆動回路に対して過電圧判別回路ＯＶと再オン回路ＲＯとを付加した点で異なっている。過電圧判別回路ＯＶは、検出抵抗Ｒｄによって検出された電圧が過電圧かどうかを判別するものであり、再オン回路ＲＯは、ＩＧＢＴのターンオフ時にこれを再オンさせるものである。
【００１２】
図１，図２の動作について図３を参照して説明する。
いま、Ｑ１が先にターンオフすると、Ｑ１のコレクタ・エミッタ間電圧ＶCEが上昇を始め、検出抵抗Ｒｄによって検出される電圧が過電圧検知レベルに達すると、過電圧判別回路ＯＶにて過電圧と判断される。これにより再オン回路ＲＯが動作するので、Ｑ１をターンオン（再オン）させる。Ｑ１が再オンすると、Ｑ１のコレクタ・エミッタ間電圧ＶCEが下降して行くので、Ｑ２がターンオフするまでの時間Δｔの間、Ｑ１に過電圧が印加されるのを防止することができる。
【００１３】
図４はこの発明の第２の実施の形態を説明するための説明図である。
これは、再オン回路ＲＯにおける再オン時のゲート電圧ＶGEを、電圧駆動型半導体素子のしきい値付近の電圧とするものである。図４の実線がこの場合のゲート電圧ＶGEを示し、再オンレベルが高い点線の場合と比べて、再オン終了後に逆バイアス電圧に戻すまでの時間が低減できるため、再オン期間中のコレクタ電流の増加を低減することができる。また、図５の再オン動作時のＩＧＢＴ動作軌跡に示すように、再オン時のゲート電圧ＶGEを電圧駆動型半導体素子のしきい値付近の電圧とすることで、素子の活性領域内で再オン動作をすることになるので、流し得るコレクタ電流がゲート電圧で制限され、再オン動作時の電流を低減できる。図５において、この発明のようにしたときの再オン電圧値ＶGE1 、再オン電圧値が高い場合をＶGE2 としたときのそれぞれの電流制限値をＩC1，ＩC2とすると、ＩC1＜ＩC2となり、流し得るコレクタ電流が低減されることが分かる。その結果、損失の増加を阻止することができる。
【００１４】
図６はこの発明の第３の実施の形態を示す構成図で、図２に示すものに対し、さらにゲート電圧クランプ回路ＧＣを付加して構成される。図７にこのようなゲート電圧クランプ回路ＧＣがある場合と無い場合の動作波形を比較して示す。すなわち、ＩＧＢＴのコレクタ・エミッタ間電圧ＶCEが過電圧検知レベルに達してから、再オン回路ＲＯが働いてゲート電圧がしきい値になり、ＩＧＢＴが再オン動作を開始するまでの時間は、ゲート電圧クランプ回路ＧＣがある場合はＴ３、ない場合はＴ４で、Ｔ３＜Ｔ４となり、ＩＧＢＴ再オン動作の高速化を図ることができる。これにより、電圧変化率（ｄｖ／ｄｔ）の高い素子の過電圧印加による素子破壊を防ぐことができる。
【００１５】
図２に示した構成で、この電力変換装置がパルス幅変調（ＰＷＭ）制御によりＩＧＢＴをオン，オフさせる場合に、前記制御装置からオフ信号が発せられ、前述の如く一方のＩＧＢＴのコレクタ・エミッタ間電圧ＶCEが過電圧検知レベルに達してから、再オン回路ＲＯが働いてゲート電圧がしきい値付近となり、このＩＧＢＴが活性領域内で再オンし、他方のＩＧＢＴのゲート電圧は逆バイアスＮ１５の状態で、前記制御装置からオン信号が発せられるときには、双方のＩＧＢＴのターンオンタイミングがずれ、その結果、他方のＩＧＢＴに過電圧が印加され素子破壊を招く恐れがあった。
【００１６】
図１１は上述の問題点を解決するこの発明の第４の実施の形態を示す構成図で、図２に示すものに対し、さらに再オン停止回路ＲＦとリセット回路ＧＲとタイマー回路ＯＴとを付加して構成される。図１２にこれらの回路が付加されたときの動作波形を示す。
【００１７】
図１，図１１の動作について図１２を参照して説明する。
いま、直列接続された電圧駆動形半導体素子Ｑ１のゲート電圧ＶGEがＱ１のしきい値付近の値に制御され、これに対して電圧駆動形半導体素子Ｑ２のゲート電圧ＶGEは通常のオフ状態である逆バイアスＮ１５になっている状態で、前記制御装置からオン信号が発せられると、タイマー回路ＯＴによりＩＧＢＴのターンオン動作を一定の時間Δｔ２だけ遅らせ、このΔｔ２の間に、再オン停止回路ＲＦにより再オン回路ＲＯの動作を停止させつつ、リセット回路ＧＲによりＩＧＢＴのゲート電圧を逆バイアスＮ１５までさげる。
【００１８】
従って、前記Δｔ２経過直前では双方のＩＧＢＴのゲート電圧は共に逆バイアスＮ１５の状態にあり、該Δｔ２経過後からＩＧＢＴのターンオン動作を開始することにより、Ｑ１，Ｑ２間のターンオンタイミングの差がより小さくでき、過電圧印加とそれによる素子破壊を防止することができる。
【００１９】
また、図２に示した構成で、この電力変換装置がパルス幅変調（ＰＷＭ）制御によりＩＧＢＴをオン，オフさせる場合に、前記制御装置からオフ信号が発せられ、前述の如く一方のＩＧＢＴのコレクタ・エミッタ間電圧ＶCEが過電圧検知レベルに達してから、再オン回路ＲＯが働いてゲート電圧がしきい値付近となり、このＩＧＢＴが活性領域内で再オンさせる。しかしながら、この再オン動作を前述のオフ信号に基づくターンオフ動作毎に繰り返すと、当該するＩＧＢＴの損失が増大するという難点があった。
【００２０】
図１３は上述の問題点を解決するこの発明の第５の実施の形態を示す構成図で、図２に示すものに対し、さらに再オン動作監視回路ＣＫとタイミング調整回路ＴＣとを付加して構成される。図１４にこれらの回路が付加されたときの動作波形を示す。
【００２１】
図１，図１３の動作について図１４を参照して説明する。
いま、直列接続された電圧駆動型半導体素子Ｑ１，Ｑ２のターンオフタイミング差Δｔ３によりＱ１のコレクタ・エミッタ電圧間電圧ＶCEが過電圧検出レベルに到達すると、再オン回路ＲＯによりＱ１のゲート電圧ＶGEがＱ１のしきい値付近の値に制御される。このとき、再オン動作監視回路ＣＫにより再オン回路ＲＯが動作したことをタイミング調整回路ＴＣに伝達され、タイミング調整回路ＴＣでは、前記制御装置からの次のオフ信号にもとづくターンオフタイミングを所定の時間遅らせるように制御し、その結果、Ｑ１，Ｑ２のターンオフタイミング差Δｔ４（＜Δｔ３）となり、Ｑ１，Ｑ２それぞれのコレクタ・エミッタ電圧間電圧ＶCEがより等しくなり、上述の再オン動作が繰り返すことを防止でき、したがって、Ｑ１の損失も軽減される。
なお、以上では電圧駆動形半導体素子としてＩＧＢＴについて説明したが、この発明はこれ以外の素子についても適用できるのは勿論である。
【００２２】
【発明の効果】
この発明によれば、各アームに電圧駆動型半導体素子が直列接続されて構成される電力変換装置で、各素子のターンオフタイミング差による電圧アンバランスが発生した場合、過電圧が印加された素子を再オンさせることで、素子破壊を防止できる利点が得られる。また、再オンの素子のゲート電圧を素子のしきい値付近の電圧レベルとすることで、再オン時の発生損失を低減することができる。さらに、素子のターンオフ時の電圧を、素子のしきい値電圧と逆バイアス電圧との間の任意の電圧に一定期間クランプさせる回路を付加することで、素子を再オンさせるまでの時間の高速化を図ることが可能となる。
【００２３】
さらに、再オン停止回路とリセット回路とタイマー回路とを付加すること、または、再オン動作監視回路とタイミング調整回路とを負荷することにより、ＰＷＭ制御される電力変換装置に好適なゲート駆動回路になる。
【図面の簡単な説明】
【図１】この発明の第１の実施の形態を示す全体構成図
【図２】この発明によるゲート駆動装置を示す構成図
【図３】図１，２の動作説明図
【図４】この発明の第２の実施の形態を説明するための説明図
【図５】再オン動作時のＩＧＢＴ軌跡の説明図
【図６】この発明の第３の実施の形態を示す構成図
【図７】図６の動作説明図
【図８】電力変換装置の従来例を示す構成図
【図９】図８で用いられるゲート駆動装置の従来例を示す構成図
【図１０】図８，９の動作を説明するための波形図
【図１１】この発明の第４の実施の形態を示す構成図
【図１２】図１１の動作を説明するための波形図
【図１３】この発明の第５の実施の形態を示す構成図
【図１４】図１３の動作を説明するための波形図
【符号の説明】
Ｑ…絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）、ＧＤＵ…ゲート駆動装置、Ｅｄ…直流電源、Ｒ…抵抗、Ｃ…コンデンサ、Ｄ…ダイオード、ＴＲ…トランジスタ、ＩＦ…インターフェイス回路、ＯＶ…過電圧判別回路、ＲＯ…再オン回路、ＧＣ…ゲート電圧クランプ回路、ＲＦ…再オン停止回路、ＧＲ…リセット回路、ＯＴ…タイマー回路、ＣＫ…再オン動作監視回路、ＴＣ…タイミング調整回路。[0001]
BACKGROUND OF THE INVENTION
This invention relates to a gate drive circuit for a voltage-driven semiconductor element in a power conversion device, particularly a power conversion device configured by connecting voltage-driven semiconductor elements in series to each arm in order to increase the voltage of the power conversion circuit. The present invention relates to a gate drive circuit for a voltage-driven semiconductor element.
[0002]
[Prior art]
FIG. 8 shows a circuit for one phase of an inverter in which IGBTs are connected in series in a conventional example in which IGBTs (insulated gate bipolar transistors) are connected in series to each arm in order to increase the voltage in the power converter.
[0003]
As shown in the figure, this circuit corresponds to IGBTs Q1, Q2 (upper arm) and Q3, Q4 (upper arm), DC power supply Ed, snubber capacitors Cs1, Cs2, snubber diodes Ds1, Ds2, snubber resistors Rs1, Rs2, and each IGBT. Charge / discharge snubber circuit (RCD snubber circuit).
[0004]
GDU1 to GDU4 are Q1 to Q4 gate drive circuits, and specifically include transistors TR1 and TR2 for turning on and off the IGBT and an interface circuit IF as shown in FIG.
[0005]
FIG. 10 shows operation waveform diagrams of FIGS.
FIG. 10 shows a case where Q2 starts the turn-off operation with a delay of time Δt after Q1 turns off. That is, when operating with IGBTs connected in series, as shown in FIG. 10, if there is a difference in the turn-off timing of the IGBTs due to variations in element characteristics or the like, an imbalance occurs in the voltage sharing of each IGBT. This is because if Q1 is turned off early, voltage is applied only to Q1 because Q2 is on. For this reason, voltage imbalance occurs. As a countermeasure, a charge / discharge snubber circuit (RCD snubber circuit in FIG. 8) is added to each IGBT to change the voltage of Q1 (the IGBT turned off first). The rate (dv / dt) is reduced, and the voltage applied to Q1 is suppressed during the period (Δt) until Q2 (IGBT turned off late) is turned off.
[0006]
[Problems to be solved by the invention]
When using IGBTs connected in series, as described above, by adding a charge / discharge snubber circuit to each IGBT, it is possible to prevent overvoltage application due to voltage imbalance when the turn-off timing is shifted and element destruction due to this. However, if the allowable time difference is to be increased, the capacitor capacity of the added snubber must be increased, and as a result, the generated loss increases, so that the shape of the resistor R increases and the device itself increases. There's a problem.
Therefore, an object of the present invention is to achieve high-speed protection of the IGBT and reduction of loss during re-on without increasing the capacitance of the snubber circuit.
[0007]
[Means for Solving the Problems]
In order to solve such a problem, according to the first aspect of the present invention, a control device that controls switching of a voltage-driven semiconductor element in a power conversion device in which a voltage-driven semiconductor element is connected in series to each arm. A drive circuit for turning on and off each of the voltage-driven semiconductor elements based on a signal from the control device, and an overvoltage determination circuit for detecting whether or not the voltage applied to the voltage-driven semiconductor element is overvoltage And a re-on circuit for turning on the voltage-driven semiconductor element again when the voltage-driven semiconductor element is turned off,
When an imbalance occurs in the voltage applied to each voltage-driven semiconductor element due to a difference in turn-off timing between the voltage-driven semiconductor elements connected in series, the voltage-driven semiconductor to which an overvoltage is applied is detected. By turning the element on again, application of overvoltage to the voltage-driven semiconductor element and element destruction based thereon are prevented.
[0008]
According to the first aspect of the present invention, by setting the gate voltage at the time of re-on to a voltage level near the threshold value of the voltage-driven semiconductor element, it is possible to reduce the loss generated at the time of re-on A clamp circuit that clamps the gate voltage at the turn-off time of each of the voltage-driven semiconductor elements to an arbitrary voltage between the threshold voltage and the reverse bias voltage for a certain time is added. Thus, the time until re-on can be increased (the invention of claim 3).
[0009]
According to a fourth aspect of the present invention, there is provided a control device for controlling the switching of the voltage-driven semiconductor element for a power conversion device in which a voltage-driven semiconductor element is connected in series to each arm; A drive circuit that drives each of the voltage-driven semiconductor elements on and off based on an off signal; an overvoltage determination circuit that detects whether a voltage applied to the voltage-driven semiconductor element is overvoltage; and the voltage-driven type A re-on circuit that turns on the voltage-driven semiconductor element again in the active region when the semiconductor element is turned off, a re-on stop circuit that stops the operation of the re-on circuit, and a reset that discharges the gate voltage of the voltage-driven semiconductor element A circuit, and a timer circuit that delays the ON operation of the voltage-driven semiconductor element by an ON signal from the control device for a certain time,
When an imbalance occurs in the applied voltage of each voltage-driven semiconductor element due to a difference in turn-off timing of each of the voltage-driven semiconductor elements connected in series when an off signal is issued from the control device, an overvoltage is generated. From the control device during the period of detecting and turning on the voltage-driven semiconductor element to which the overvoltage is applied in the active region to prevent the application of the overvoltage to the voltage-driven semiconductor element and the element destruction based thereon When an on signal is generated, the re-on stop circuit and the reset circuit are simultaneously operated to discharge the gate voltage of the voltage-driven semiconductor element, and then the voltage-driven semiconductor element is started to be turned on. By applying an overvoltage to each voltage-driven semiconductor element due to a difference in turn-on timing of each of the series-connected voltage-driven semiconductor elements And so as to prevent the device destruction based on it.
[0010]
Furthermore, in the invention of claim 5, for a power conversion device in which a voltage-driven semiconductor element is connected in series to each arm, a control device that controls switching of the voltage-driven semiconductor element, A drive circuit that drives each of the voltage-driven semiconductor elements on and off based on an off signal; an overvoltage determination circuit that detects whether a voltage applied to the voltage-driven semiconductor element is overvoltage; and the voltage-driven type A re-on circuit that turns on the voltage-driven semiconductor element again in the active region when the semiconductor element is turned off, a re-on operation monitoring circuit that monitors the operation of the re-on circuit, and the next turn-off when the re-on circuit operates A timing adjustment circuit for delaying the timing by a predetermined time;
When an imbalance occurs in the applied voltage of each voltage-driven semiconductor element due to a difference in turn-off timing of each of the voltage-driven semiconductor elements connected in series when an off signal is issued from the control device, an overvoltage is generated. The voltage-driven semiconductor element to which the overvoltage is applied is turned on again in the active region, and when the next off signal is issued from the control device after the re-on operation, the turn-off timing based on the off signal is set. By delaying for a predetermined time, the voltage sharing of each of the voltage-driven semiconductor elements connected in series is made uniform, and overvoltage application to each voltage-driven semiconductor element and element destruction based thereon are prevented. .
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing a first embodiment of the present invention, which is an example in which two IGBTs are connected in series to the upper and lower arms as in FIG. In other words, the RCD snubber circuit of each IGBT is apparently an RC snubber circuit. However, as shown in FIG. 2, the gate driving device GDU has an overvoltage discrimination circuit OV with respect to the gate driving circuit shown in FIG. The difference is that a re-ON circuit RO is added. The overvoltage discriminating circuit OV discriminates whether or not the voltage detected by the detection resistor Rd is an overvoltage, and the re-on circuit RO re-turns on the IGBT when it is turned off.
[0012]
The operation of FIGS. 1 and 2 will be described with reference to FIG.
Now, when Q1 is turned off earlier, Q1 begin to rise collector-emitter voltage V CE of the voltage detected by the detection resistor Rd has reached the overvoltage detection level, it is determined that the overvoltage at overvoltage determining circuit OV . As a result, the re-on circuit RO operates, so that Q1 is turned on (re-on). When Q1 is turned on again, the collector-emitter voltage V CE of Q1 decreases, so that it is possible to prevent an overvoltage from being applied to Q1 during the time Δt until Q2 is turned off.
[0013]
FIG. 4 is an explanatory diagram for explaining a second embodiment of the present invention.
This is to set the gate voltage V GE at the time of re-on in the re-on circuit RO to a voltage near the threshold value of the voltage-driven semiconductor element. The solid line in FIG. 4 shows the gate voltage V GE in this case. Compared to the dotted line with a high re-on level, the time until the reverse bias voltage is restored after re-on can be reduced. An increase in current can be reduced. Further, as shown in the IGBT operation locus at the time of the re-on operation in FIG. 5, the gate voltage V GE at the time of the re-on is set to a voltage in the vicinity of the threshold value of the voltage-driven semiconductor element, so that in the active region of the element. Since the re-on operation is performed, the collector current that can flow is limited by the gate voltage, and the current during the re-on operation can be reduced. In FIG. 5, assuming that the current limit values are I C1 and I C2 when the re-on voltage value V GE1 and V GE2 when the re-on voltage value is high in the case of the present invention, respectively, I C1 < It can be seen that I C2 and the collector current that can flow is reduced. As a result, an increase in loss can be prevented.
[0014]
FIG. 6 is a block diagram showing a third embodiment of the present invention, which is configured by adding a gate voltage clamp circuit GC to that shown in FIG. FIG. 7 shows a comparison of operation waveforms with and without such a gate voltage clamp circuit GC. That is, the time from when the IGBT collector-emitter voltage V CE reaches the overvoltage detection level to when the re-ON circuit RO is activated and the gate voltage becomes a threshold value and the IGBT starts the re-ON operation is the gate time. T3 when the voltage clamp circuit GC is present and T4 when it is not present, and T3 <T4, so that the IGBT re-on operation can be speeded up. Thereby, element destruction due to overvoltage application of an element having a high voltage change rate (dv / dt) can be prevented.
[0015]
In the configuration shown in FIG. 2, when the power conversion device turns on / off the IGBT by pulse width modulation (PWM) control, an off signal is generated from the control device, and the collector / emitter of one IGBT as described above. After the inter-voltage V CE reaches the overvoltage detection level, the re-ON circuit RO operates and the gate voltage becomes near the threshold value. This IGBT is turned on again in the active region, and the gate voltage of the other IGBT is the reverse bias N15. In this state, when an ON signal is issued from the control device, the turn-on timings of both IGBTs are shifted. As a result, an overvoltage is applied to the other IGBT, which may cause element destruction.
[0016]
FIG. 11 is a block diagram showing a fourth embodiment of the present invention that solves the above-mentioned problems. A re-on stop circuit RF, a reset circuit GR, and a timer circuit OT are further added to that shown in FIG. Configured. FIG. 12 shows operation waveforms when these circuits are added.
[0017]
1 and 11 will be described with reference to FIG.
Now, the gate voltage V GE of the voltage-driven semiconductor element Q1 connected in series is controlled to a value near the threshold value of Q1, whereas the gate voltage V GE of the voltage-driven semiconductor element Q2 is in a normal OFF state. When the ON signal is issued from the control device in the state of the reverse bias N15, the timer circuit OT delays the IGBT turn-on operation by a fixed time Δt2, and during this Δt2, the re-on stop circuit RF By stopping the operation of the re-ON circuit RO, the gate voltage of the IGBT is reduced to the reverse bias N15 by the reset circuit GR.
[0018]
Therefore, the gate voltages of both IGBTs are in the reverse bias N15 state immediately before the lapse of Δt2, and the turn-on timing difference between Q1 and Q2 is smaller by starting the IGBT turn-on operation after the lapse of Δt2. In addition, it is possible to prevent application of overvoltage and element breakdown due to it.
[0019]
Further, in the configuration shown in FIG. 2, when the power conversion device turns on / off the IGBT by pulse width modulation (PWM) control, an off signal is generated from the control device, and as described above, the collector of one IGBT After the emitter-to-emitter voltage V CE reaches the overvoltage detection level, the re-on circuit RO operates to make the gate voltage near the threshold value, and this IGBT is turned on again in the active region. However, if this re-on operation is repeated for each turn-off operation based on the aforementioned off signal, there is a problem that the loss of the IGBT concerned increases.
[0020]
FIG. 13 is a block diagram showing a fifth embodiment of the present invention for solving the above-mentioned problems. A re-ON operation monitoring circuit CK and a timing adjustment circuit TC are further added to that shown in FIG. Composed. FIG. 14 shows operation waveforms when these circuits are added.
[0021]
The operation of FIGS. 1 and 13 will be described with reference to FIG.
Now, when the collector-emitter voltage across the voltage V CE of the turn-off timing difference Δt3 by Q1 of the series-connected voltage-driven semiconductor elements Q1, Q2 reaches the overvoltage detection level, the gate voltage V GE of Q1 by re-on circuit RO is It is controlled to a value near the threshold value of Q1. At this time, the operation of the re-ON circuit RO is transmitted to the timing adjustment circuit TC by the re-ON operation monitoring circuit CK, and the timing adjustment circuit TC sets the turn-off timing based on the next OFF signal from the control device for a predetermined time. As a result, the turn-off timing difference Δt 4 (<Δt 3) between Q 1 and
In the above description, the IGBT is described as the voltage-driven semiconductor element. However, the present invention is naturally applicable to other elements.
[0022]
【The invention's effect】
According to the present invention, in a power converter configured by connecting voltage-driven semiconductor elements in series to each arm, when a voltage imbalance occurs due to a difference in turn-off timing of each element, the element to which the overvoltage is applied is regenerated. By turning it on, the advantage of preventing element destruction can be obtained. In addition, by setting the gate voltage of the re-on element to a voltage level in the vicinity of the threshold value of the element, it is possible to reduce generation loss at the time of re-on. Furthermore, by adding a circuit that clamps the voltage at the time of device turn-off to an arbitrary voltage between the threshold voltage of the device and the reverse bias voltage for a certain period of time, the time until the device is turned on again is increased. Can be achieved.
[0023]
Furthermore, by adding a re-on stop circuit, a reset circuit, and a timer circuit, or by loading a re-on operation monitoring circuit and a timing adjustment circuit, a gate drive circuit suitable for a power converter that is PWM-controlled Become.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram showing a first embodiment of the present invention. FIG. 2 is a configuration diagram showing a gate driving device according to the present invention. FIG. 3 is an operation explanatory diagram of FIGS. FIG. 5 is an explanatory diagram for explaining an IGBT trajectory during a re-on operation. FIG. 6 is a block diagram showing a third embodiment of the present invention. FIG. 8 is a block diagram showing a conventional example of a power converter. FIG. 9 is a block diagram showing a conventional example of a gate driving device used in FIG. 8. FIG. 10 is a block diagram showing the operations of FIGS. FIG. 11 is a block diagram showing a fourth embodiment of the present invention. FIG. 12 is a waveform diagram for explaining the operation of FIG. 11. FIG. 13 is a fifth embodiment of the present invention. FIG. 14 is a waveform diagram for explaining the operation of FIG. 13;
Q: Insulated gate bipolar transistor (IGBT), GDU: Gate drive device, Ed: DC power supply, R ... Resistance, C ... Capacitor, D ... Diode, TR ... Transistor, IF ... Interface circuit, OV ... Overvoltage discrimination circuit, RO ... Re-on circuit, GC: gate voltage clamp circuit, RF: re-on stop circuit, GR ... reset circuit, OT ... timer circuit, CK ... re-on operation monitoring circuit, TC ... timing adjustment circuit.
Claims (5)
前記各直列接続された電圧駆動型半導体素子のターンオフタイミングの差により、各電圧駆動型半導体素子の印加電圧にアンバランスが発生したときは、過電圧を検出し、過電圧が印加された電圧駆動型半導体素子を再オンさせることにより、電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止することを特徴とする電圧駆動型半導体素子のゲート駆動回路。A control device that controls switching of the voltage-driven semiconductor element for a power conversion device in which a voltage-driven semiconductor element is connected in series to each arm, and each of the voltage-driven semiconductor elements based on a signal from the control device A drive circuit for driving on and off, an overvoltage discrimination circuit for detecting a voltage applied to the voltage-driven semiconductor element and determining whether or not it is an overvoltage, and a voltage-driven semiconductor element again when the voltage-driven semiconductor element is turned off And a re-on circuit to turn on,
When an imbalance occurs in the voltage applied to each voltage-driven semiconductor element due to a difference in turn-off timing between the voltage-driven semiconductor elements connected in series, the voltage-driven semiconductor to which an overvoltage is applied is detected. A gate drive circuit for a voltage-driven semiconductor element, wherein an overvoltage is applied to the voltage-driven semiconductor element and element destruction based on the overvoltage is prevented by turning on the element again.
前記制御装置からオフ信号が発せられたときに前記各直列接続された電圧駆動型半導体素子のターンオフタイミングの差により、各電圧駆動型半導体素子の印加電圧にアンバランスが発生したときは、過電圧を検出し、過電圧が印加された電圧駆動型半導体素子を活性領域内で再オンさせて、該電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止している期間中に
前記制御装置からオン信号が発せられたときには、前記再オン停止回路とリセット回路とを同時に動作させて前記電圧駆動型半導体素子のゲート電圧を放電させた後に、前記電圧駆動型半導体素子をオン動作を開始させることにより、前記各直列接続された電圧駆動型半導体素子のターンオンタイミングの差による各電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止することを特徴とする電圧駆動型半導体素子のゲート駆動回路。For a power conversion device in which voltage-driven semiconductor elements are connected in series to each arm, a control device that controls switching of the voltage-driven semiconductor elements, and each voltage drive based on an on / off signal from the control device Drive circuit for turning on and off the semiconductor device, an overvoltage determination circuit for detecting whether the voltage applied to the voltage drive semiconductor device is overvoltage, and voltage driving again when the voltage drive semiconductor device is turned off A re-on circuit for turning on the semiconductor device in the active region, a re-on stop circuit for stopping the operation of the re-on circuit, a reset circuit for discharging the gate voltage of the voltage-driven semiconductor device, and the control device A timer circuit for delaying the ON operation of the voltage-driven semiconductor element by the ON signal for a certain period of time;
When an imbalance occurs in the applied voltage of each voltage-driven semiconductor element due to a difference in turn-off timing of each of the voltage-driven semiconductor elements connected in series when an off signal is issued from the control device, an overvoltage is generated. From the control device during the period of detecting and turning on the voltage-driven semiconductor element to which the overvoltage is applied in the active region to prevent the application of the overvoltage to the voltage-driven semiconductor element and the element destruction based thereon When an on signal is generated, the re-on stop circuit and the reset circuit are simultaneously operated to discharge the gate voltage of the voltage-driven semiconductor element, and then the voltage-driven semiconductor element is started to be turned on. By applying an overvoltage to each voltage-driven semiconductor element due to a difference in turn-on timing of each of the series-connected voltage-driven semiconductor elements And the gate drive circuit of a voltage driving type semiconductor element characterized in that to prevent the device destruction based on it.
前記制御装置からオフ信号が発せられたときに前記各直列接続された電圧駆動型半導体素子のターンオフタイミングの差により、各電圧駆動型半導体素子の印加電圧にアンバランスが発生したときは、過電圧を検出し、過電圧が印加された電圧駆動型半導体素子を活性領域内で再オンさせ、この再オン動作後、該制御装置から次のオフ信号が発せられたときには、このオフ信号にもとづくターンオフタイミングを所定の時間遅らせることにより、前記各直列接続された電圧駆動型半導体素子それぞれの電圧分担を均一化させて、各電圧駆動型半導体素子への過電圧印加およびそれにもとづく素子破壊を防止することを特徴とする電圧駆動型半導体素子のゲート駆動回路。For a power conversion device in which voltage-driven semiconductor elements are connected in series to each arm, a control device that controls switching of the voltage-driven semiconductor elements, and each voltage drive based on an on / off signal from the control device Drive circuit for turning on and off the semiconductor device, an overvoltage determination circuit for detecting whether the voltage applied to the voltage drive semiconductor device is overvoltage, and voltage driving again when the voltage drive semiconductor device is turned off -On circuit that turns on the semiconductor device in the active region, a re-on operation monitoring circuit that monitors the operation of the re-on circuit, and a timing adjustment that delays the next turn-off timing by a predetermined time when the re-on circuit operates Circuit and
When an imbalance occurs in the applied voltage of each voltage-driven semiconductor element due to a difference in turn-off timing of each of the voltage-driven semiconductor elements connected in series when an off signal is issued from the control device, an overvoltage is generated. The voltage-driven semiconductor element to which the overvoltage is applied is turned on again in the active region, and when the next off signal is issued from the control device after the re-on operation, the turn-off timing based on the off signal is set. By delaying for a predetermined time, the voltage sharing of each of the voltage-driven semiconductor elements connected in series is made uniform, and overvoltage application to each voltage-driven semiconductor element and element destruction based thereon are prevented. A gate drive circuit for a voltage driven semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12989399A JP3724255B2 (en) | 1998-06-26 | 1999-05-11 | Gate drive circuit for voltage driven semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19510998 | 1998-06-26 | ||
| JP11-2487 | 1999-01-08 | ||
| JP10-195109 | 1999-01-08 | ||
| JP248799 | 1999-01-08 | ||
| JP12989399A JP3724255B2 (en) | 1998-06-26 | 1999-05-11 | Gate drive circuit for voltage driven semiconductor device |
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| JP2000262068A JP2000262068A (en) | 2000-09-22 |
| JP3724255B2 true JP3724255B2 (en) | 2005-12-07 |
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| JP5036466B2 (en) * | 2007-09-20 | 2012-09-26 | 東芝三菱電機産業システム株式会社 | Redundant control power conversion system and its soundness confirmation method |
| JP6111726B2 (en) * | 2013-02-19 | 2017-04-12 | 富士電機株式会社 | Control method of multi-level power conversion circuit |
| US10432101B2 (en) | 2016-08-10 | 2019-10-01 | Mitsubishi Electric Corporation | Power conversion apparatus |
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