JP2001231247A - Gate driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the destruction of any of a plurality of voltage-drive semiconductor elements connected in series, by restraining voltage unbalancing due to a difference between timings of turning on and off the respective elements and the application of overvoltage to any of the elements. SOLUTION: When an overvoltage is applied to one voltage drive semiconductor element which has turned off previously, the timing for the next turn-off is delayed by means of the timing difference in response to a detection signal from a constant-voltage element current detection circuit which detects the current flowing through the constant-voltage element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit for a voltage-driven semiconductor device used in a power converter or the like, and more particularly, to a voltage-driven semiconductor device connected in series to each arm to output a high voltage. The present invention relates to a method of driving a gate of a voltage-driven semiconductor device of a power converter having a configuration as described above.

[0002]

2. Description of the Related Art FIG. 3 shows a voltage-driven semiconductor device (here, IGBT:
An example using an insulated gate bipolar transistor is shown)
Shows a circuit for one phase of the power conversion device when is connected in series to each arm. In FIG. 3, Q1 to Q4 are IGBT, E
d is a DC power supply, Cs1 and Cs2 are snubber capacitors, D
S1 and Ds2 are snubber diodes, Rs1 and Rs2 are snubber resistors, and GDU1 to GDU4 are gate drive circuits for Q1 to Q4.

FIG. 4 shows that after Q1 in FIG. 3 is turned off,
FIG. 9 is a diagram showing gate-emitter voltages and collector-emitter waveforms of Q1 and Q2 when Q2 turns off with a delay of time Δt. In this way, IGBT
When the IGBTs are driven in series and a difference occurs in the turn-off timing of the IGBT due to variations in element characteristics or the like, imbalance occurs in the voltage sharing of each IGBT.
This means that while Q1 turns off early,
This is because the voltage is applied only to Q1 since 2 is still on.

In order to eliminate such imbalance of voltage application, a gate drive circuit as shown in FIG. 5 is sometimes used. In the circuit of FIG. 5, TR1 and TR2 are I
A transistor for turning on and off the GBT, IF is an interface circuit, and ZD is a collector-gate constant voltage element for clamping the collector voltage of the IGBT to a predetermined value.

FIG. 6 is an operation waveform diagram of FIG. When the IGBT shown in FIG. 5 is Q1 in FIG. 3, this IGBT
IGBT (Q2 not shown) with (Q1) connected in series
When the turn-off is made earlier by the time Δt, the collector-emitter voltage VCE of Q1 starts to rise, and this voltage becomes ZD
, A current flows through the gate of Q1 through ZD. With this current, the gate-emitter voltage is charged in the forward bias direction, and the collector-emitter voltage is clamped to an avalanche voltage value of approximately ZD. Therefore, it is possible to prevent application of an overvoltage equal to or higher than the avalanche voltage of ZD to Q1 at least.

[0006]

When the gate drive circuit shown in FIG. 5 is used, when voltage-driven semiconductor devices such as IGBTs are connected in series, when a turn-off timing is shifted, overvoltage application due to voltage imbalance and It is possible to temporarily prevent the device from being destroyed. However, since the voltage clamp operation of the constant voltage element is repeated every time the turn-off operation is performed in a state where the difference between the turn-off timings is constant, there is a problem that the loss generated in the voltage-driven semiconductor element and the constant voltage element increases. there were.

Accordingly, the object of the present invention is as shown in FIG.
An object of the present invention is to eliminate a turn-off switching timing difference while suppressing overvoltage of a voltage-driven semiconductor element using a constant-voltage element, and to reduce a loss generated in the voltage-driven semiconductor element and the constant-voltage element.

[0008]

In order to achieve the above object, according to the present invention, in a power converter in which a voltage-driven semiconductor element is connected in series to each arm, each voltage-driven semiconductor element of the arm is simultaneously connected. On and off,
A constant voltage element is provided between the collector and the gate of each voltage driven semiconductor element, and a constant voltage element current detection circuit for detecting a current flowing through the constant voltage element is provided. When the voltage applied to one of the elements reaches the avalanche voltage of the constant voltage element and detects that a current flows through the constant voltage element, the next turn-off switching timing of the one semiconductor element is delayed for a certain time. The voltage application to the voltage-driven semiconductor elements connected in series is made uniform.

[0009]

FIG. 1 shows an embodiment of the present invention.
The difference from the gate drive circuit shown in FIG. 5 is that a current detection circuit CK of a constant voltage element and a timing adjustment circuit TC for delaying the next turn-off switching timing by a certain time when a current is detected by CK are added. .

FIG. 2 shows the operation of FIG. When the collector-emitter voltage VCE1 of Q1 reaches the avalanche voltage of the constant voltage element ZD1 due to the difference Δt1 between the turn-off switching timings of the voltage-driven semiconductor elements Q1 and Q2 connected in series, a current flows through the gate of Q1 via ZD1. Flows. At this time, the current detection circuit CK of the constant voltage element
Accordingly, the voltage clamp operation by the constant voltage element is input to the timing adjustment circuit as a detection signal, and the control is performed so that the switching timing is delayed by a certain time at the next turn-off.

Assuming that the difference between the turn-off switching timings of the first Q1 and Q2 is Δt1, the adjustment time (constant value) is Δt ′, and the next timing difference is Δt2, Δt2 = Δt1−Δt ′ (< Δt1) holds. Δt2 gradually decreases until the clamp operation by the constant voltage element stops, and the timing adjustment operation is repeated. Here, the turn-off switching timing difference is Δt at the time when the clamp operation is lost.
Is the timing difference maintained in the subsequent turn-off.

As a result, the series-connected collector-emitter voltages are equalized, and the voltage clamp operation can be prevented from being permanently repeated. Here, if the adjustment time Δt ′ is too large, the adjusted timing difference is reversed. That is, when the sign of the next timing difference Δt2 is reversed and Δt ′ is used such that the absolute value of Δt2 exceeds Δt1, the other element is conversely applied with an overvoltage. , Causing a clamping operation.

In the case where power conversion is performed by connecting IGBTs in series and turning them on and off simultaneously, the turn-off timing difference is generally at a level of several hundred nS at the maximum. Adjustment time is 10-20
It has been found that nS is desirable. This is because to prevent the reversal phenomenon, it is only necessary to set an adjustment time of a few nS or shorter, but if it is too short, the turn-off timing difference is improved and the time until the clamping operation is eliminated becomes longer. It is because.

[0014]

As described above, according to the present invention, in a power converter in which voltage-driven semiconductor elements are connected in series to each arm, control for simultaneously turning on and off each voltage-driven semiconductor element of the arm is provided. In doing so, when an overvoltage of the voltage applied to one of the voltage-driven semiconductor elements is detected due to a shift in the turn-off switching timing, the next turn-off switching timing of one of the semiconductor elements is delayed by a certain time. In addition, it is possible to prevent application of an overvoltage to the semiconductor element, to reduce a loss generated in the semiconductor element, and to prevent a loss and an element deterioration generated in a constant voltage element for detecting overvoltage application.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the embodiment of the present invention.

FIG. 3 is a circuit configuration diagram of a conventional power converter.

FIG. 4 is an operation waveform diagram of the circuit configuration diagram of FIG. 3;

FIG. 5 is a circuit diagram of a second conventional circuit.

FIG. 6 is an operation waveform diagram of the circuit configuration diagram of FIG. 5;

[Explanation of symbols]

1, 2, device chip, 3, 4, 5, ... electrode, 6, 7, ...
Substrate, 8, 9 ... wire bonding, 10 ... dielectric, 1
DESCRIPTION OF SYMBOLS 1 ... Package, 30 ... Snubber capacitor, Cd ... Electrolytic capacitor, Cs ... Snubber capacitor, T1-T6 ... Transistor, D1-D6 ... Diode, A, B ... Power connection electrode, U, V, W ... Load connection electrode , C1, C2 ...
Transistor output capacity

Claims (1)

[Claims] 1. A power converter comprising a plurality of voltage-driven semiconductor elements connected in series to each arm, wherein when simultaneously turning on and off each of the voltage-driven semiconductor elements of the arm, a collector of each of the voltage-driven semiconductor elements is provided. A constant voltage element between the gates, and a constant voltage element current detection circuit for detecting a current flowing through the constant voltage element, respectively, and a voltage applied to one of the voltage driven semiconductor elements due to a shift in turn-off switching timing. When the voltage reaches the avalanche voltage of the constant voltage element and it is detected that a current flows through the constant voltage element, the next turn-off switching timing of the one semiconductor element is delayed for a certain time, and the voltage-driven semiconductor connected in series A method of driving a gate for a voltage-driven semiconductor device, wherein voltage application to the device is made uniform.