JP4442353B2 - 配線基板の製造方法 - Google Patents
配線基板の製造方法 Download PDFInfo
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- JP4442353B2 JP4442353B2 JP2004219695A JP2004219695A JP4442353B2 JP 4442353 B2 JP4442353 B2 JP 4442353B2 JP 2004219695 A JP2004219695 A JP 2004219695A JP 2004219695 A JP2004219695 A JP 2004219695A JP 4442353 B2 JP4442353 B2 JP 4442353B2
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- wiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
図1は、本発明の第1実施形態に係る配線基板100の概略断面構成を示す図であり、図2は、この配線基板100に各種部品を実装した状態を示す概略断面図である。
配線基板100の本体をなす基板10は、本例ではセラミック積層基板10であり、この積層基板10は、個々についてその表面および内部に配線層が形成された複数のセラミック層11、12、13、14を積層して形成されたものである。
次に、限定するものではないが、上記図1に示される配線基板100の製造方法および上記図2に示される実装構造の組み付け方法の一具体例について説明する。
上記実施形態では、大電流用ランド15aのメッキ層152は、無電解銅メッキ膜の上に電気銅メッキ膜を積層させた構成とし、この構成における製造方法について主として述べた。
図9は、本発明の第3実施形態に係る製造方法の要部を示す概略断面図である。上記実施形態との相違点を述べる。
なお、大電流用ランド15aのメッキ層152を、無電解銅メッキ膜の上に電気銅メッキ膜を積層させた構成とする場合には、電気メッキは、厚膜抵抗体23の形成後に行ってもよいし、上記金メッキの前後に行ってもよい。さらには、電気銅メッキ膜上の金メッキの形成は行ってもよいし、行わなくてもよい。
15…配線としての上面ランド、
15a…電気メッキにより形成される配線の一部としての大電流用ランド、
15b…小電流用ランド、16…配線としての下面ランド、110…電極。
Claims (2)
- 基板(10)の表面に、無電解メッキからなる配線(15、16)を形成してなる配線基板の製造方法において、
前記基板(10)として、複数のセラミック層(11〜14)を積層してなるとともに、内部に内層配線(17、18)が設けられてなるものを用い、
前記基板(10)のうち前記配線(15、16)を形成すべき部位に、無電解メッキにより膜を形成した後、この膜の表面の一部に電気メッキを施すことにより、前記配線(15、16)を形成するものであり、
前記基板(10)における最終的に切断除去される端部に、前記電気メッキを行うための電極(110)を形成し、前記電極(110)と前記内層配線(17、18)とを電気的に接続し、前記内層配線(17、18)を介して前記電極(110)と前記電気メッキを行う部位とを結線した後、前記電気メッキを行うことを特徴とする配線基板の製造方法。 - 基板(10)の表面に、無電解メッキからなる配線(15、16)を形成してなる配線基板の製造方法において、
前記基板(10)として、複数のセラミック層(11〜14)を積層してなるとともに、内部に内層配線(17、18)が設けられてなるものを用い、
前記基板(10)のうち前記配線(15、16)を形成すべき部位の一部に、電気メッキにより膜を形成した後、前記基板(10)のうち前記配線(15、16)を形成すべき部位のすべてに無電解メッキを施すことにより、前記配線(15、16)を形成するものであり、
前記基板(10)における最終的に切断除去される端部に、前記電気メッキを行うための電極(110)を形成し、前記電極(110)と前記内層配線(17、18)とを電気的に接続し、前記内層配線(17、18)を介して前記電極(110)と前記電気メッキを行う部位とを結線した後、前記電気メッキを行うことを特徴とする配線基板の製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2004219695A JP4442353B2 (ja) | 2004-07-28 | 2004-07-28 | 配線基板の製造方法 |
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JP2004219695A JP4442353B2 (ja) | 2004-07-28 | 2004-07-28 | 配線基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2006041226A JP2006041226A (ja) | 2006-02-09 |
JP4442353B2 true JP4442353B2 (ja) | 2010-03-31 |
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Application Number | Title | Priority Date | Filing Date |
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JP2004219695A Expired - Fee Related JP4442353B2 (ja) | 2004-07-28 | 2004-07-28 | 配線基板の製造方法 |
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JP (1) | JP4442353B2 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5172275B2 (ja) * | 2007-10-26 | 2013-03-27 | パナソニック株式会社 | 部品内蔵プリント配線基板および部品内蔵プリント配線基板の製造方法 |
JP2010141252A (ja) | 2008-12-15 | 2010-06-24 | Mitsubishi Electric Corp | エッジコネクタおよびその製造方法 |
JP2010192903A (ja) * | 2010-02-23 | 2010-09-02 | Toshiba Corp | 電子機器 |
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2004
- 2004-07-28 JP JP2004219695A patent/JP4442353B2/ja not_active Expired - Fee Related
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