JP4439082B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP4439082B2 JP4439082B2 JP2000167643A JP2000167643A JP4439082B2 JP 4439082 B2 JP4439082 B2 JP 4439082B2 JP 2000167643 A JP2000167643 A JP 2000167643A JP 2000167643 A JP2000167643 A JP 2000167643A JP 4439082 B2 JP4439082 B2 JP 4439082B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- read
- write
- data line
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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- TXJZRSRTYPUYRW-NQIIRXRSSA-N methyl (1s,3r)-2-(2-chloroacetyl)-1-(4-methoxycarbonylphenyl)-1,3,4,9-tetrahydropyrido[3,4-b]indole-3-carboxylate Chemical compound C1([C@H]2C3=C(C4=CC=CC=C4N3)C[C@@H](N2C(=O)CCl)C(=O)OC)=CC=C(C(=O)OC)C=C1 TXJZRSRTYPUYRW-NQIIRXRSSA-N 0.000 description 1
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Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
- G11C29/848—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by adjacent switching
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/50—Peripheral circuit region structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Landscapes
- Dram (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000167643A JP4439082B2 (ja) | 2000-06-05 | 2000-06-05 | 半導体記憶装置 |
| US09/781,238 US6381167B2 (en) | 2000-06-05 | 2001-02-13 | Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
| US10/118,126 US6549445B2 (en) | 2000-06-05 | 2002-04-09 | Semiconductor memory device including plurality of global data lines in parallel arrangement with low parasitic capacitance, and fabrication method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000167643A JP4439082B2 (ja) | 2000-06-05 | 2000-06-05 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001344965A JP2001344965A (ja) | 2001-12-14 |
| JP2001344965A5 JP2001344965A5 (enExample) | 2007-07-05 |
| JP4439082B2 true JP4439082B2 (ja) | 2010-03-24 |
Family
ID=18670771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000167643A Expired - Fee Related JP4439082B2 (ja) | 2000-06-05 | 2000-06-05 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US6381167B2 (enExample) |
| JP (1) | JP4439082B2 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4439082B2 (ja) * | 2000-06-05 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| JP4540889B2 (ja) * | 2001-07-09 | 2010-09-08 | 富士通セミコンダクター株式会社 | 半導体メモリ |
| JP2003347431A (ja) * | 2002-05-29 | 2003-12-05 | Fujitsu Ltd | 半導体記憶装置 |
| DE60205344D1 (de) * | 2002-05-31 | 2005-09-08 | St Microelectronics Srl | Teststruktur zur Messung des Kontakt-Gate-Abstandes in nichtflüchtigen Speichern und zugehöriges Testverfahren |
| TW589753B (en) * | 2003-06-03 | 2004-06-01 | Winbond Electronics Corp | Resistance random access memory and method for fabricating the same |
| US7110319B2 (en) * | 2004-08-27 | 2006-09-19 | Micron Technology, Inc. | Memory devices having reduced coupling noise between wordlines |
| KR100615577B1 (ko) * | 2004-09-10 | 2006-08-25 | 삼성전자주식회사 | 반도체 메모리 장치 및 이 장치의 신호 라인 배치 방법 |
| JP2006179109A (ja) * | 2004-12-22 | 2006-07-06 | Matsushita Electric Ind Co Ltd | メモリ回路 |
| KR100630733B1 (ko) * | 2005-01-12 | 2006-10-02 | 삼성전자주식회사 | 전력소모를 감소시킬 수 있는 워드라인 인에이블 신호라인 배치 구조를 갖는 반도체 메모리장치 및 이의워드라인 인에이블 신호 라인 배치방법 |
| US20060182187A1 (en) * | 2005-02-11 | 2006-08-17 | Likovich Robert B Jr | Automatic reconfiguration of an I/O bus to correct for an error bit |
| KR100653715B1 (ko) | 2005-06-17 | 2006-12-05 | 삼성전자주식회사 | 적어도 하나의 개구부를 갖는 최상부 금속층을 구비하는반도체 소자들 및 그 제조방법들 |
| JP4756581B2 (ja) | 2005-07-21 | 2011-08-24 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
| US8378448B2 (en) * | 2009-03-18 | 2013-02-19 | International Business Machines Corporation | Chip inductor with frequency dependent inductance |
| US7940544B2 (en) * | 2009-04-30 | 2011-05-10 | Kabushiki Kaisha Toshiba | Memory system having multiple vias at junctions between traces |
| CN104580558B (zh) * | 2013-10-17 | 2019-05-07 | 中兴通讯股份有限公司 | 一种终端盖体及终端 |
| JP2020145372A (ja) * | 2019-03-08 | 2020-09-10 | キオクシア株式会社 | 半導体記憶装置 |
| JP2022125651A (ja) * | 2021-02-17 | 2022-08-29 | キオクシア株式会社 | 半導体記憶装置 |
| JP7392183B2 (ja) * | 2021-03-24 | 2023-12-05 | 長江存儲科技有限責任公司 | 冗長バンクを使用した故障メインバンクの修理を伴うメモリデバイス |
| US20240221823A1 (en) * | 2022-12-30 | 2024-07-04 | Atomera Incorporated | Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers And Methods For Operating Same |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0512883A (ja) | 1991-07-05 | 1993-01-22 | Nippon Steel Corp | シーケンシヤルメモリ |
| JPH07130163A (ja) * | 1993-11-01 | 1995-05-19 | Matsushita Electron Corp | 半導体メモリ |
| JP3253462B2 (ja) | 1994-09-07 | 2002-02-04 | 富士通株式会社 | 半導体記憶装置 |
| JP2817836B2 (ja) * | 1995-11-30 | 1998-10-30 | 日本電気株式会社 | 半導体メモリ装置 |
| JPH1027467A (ja) | 1996-07-12 | 1998-01-27 | Sony Corp | 半導体装置 |
| US6177699B1 (en) * | 1998-03-19 | 2001-01-23 | Lsi Logic Corporation | DRAM cell having a verticle transistor and a capacitor formed on the sidewalls of a trench isolation |
| JP4439082B2 (ja) * | 2000-06-05 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
-
2000
- 2000-06-05 JP JP2000167643A patent/JP4439082B2/ja not_active Expired - Fee Related
-
2001
- 2001-02-13 US US09/781,238 patent/US6381167B2/en not_active Expired - Lifetime
-
2002
- 2002-04-09 US US10/118,126 patent/US6549445B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US20020110016A1 (en) | 2002-08-15 |
| US6381167B2 (en) | 2002-04-30 |
| US20010052599A1 (en) | 2001-12-20 |
| US6549445B2 (en) | 2003-04-15 |
| JP2001344965A (ja) | 2001-12-14 |
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