JP4416843B2 - 集積回路においてトレンチアイソレーション構造を形成する方法 - Google Patents

集積回路においてトレンチアイソレーション構造を形成する方法 Download PDF

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Publication number
JP4416843B2
JP4416843B2 JP10184596A JP10184596A JP4416843B2 JP 4416843 B2 JP4416843 B2 JP 4416843B2 JP 10184596 A JP10184596 A JP 10184596A JP 10184596 A JP10184596 A JP 10184596A JP 4416843 B2 JP4416843 B2 JP 4416843B2
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Prior art keywords
trench
dielectric layer
layer
forming
etched
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JP10184596A
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Japanese (ja)
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JPH08279552A5 (enExample
JPH08279552A (ja
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アサンガ・エイチ・ペレラ
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NXP USA Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
JP10184596A 1995-04-04 1996-04-01 集積回路においてトレンチアイソレーション構造を形成する方法 Expired - Fee Related JP4416843B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/416,243 US5786263A (en) 1995-04-04 1995-04-04 Method for forming a trench isolation structure in an integrated circuit
US08/416,243 1995-04-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007001007A Division JP4168073B2 (ja) 1995-04-04 2007-01-09 集積回路においてトレンチアイソレーション構造を形成する方法

Publications (3)

Publication Number Publication Date
JPH08279552A JPH08279552A (ja) 1996-10-22
JPH08279552A5 JPH08279552A5 (enExample) 2005-08-11
JP4416843B2 true JP4416843B2 (ja) 2010-02-17

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Application Number Title Priority Date Filing Date
JP10184596A Expired - Fee Related JP4416843B2 (ja) 1995-04-04 1996-04-01 集積回路においてトレンチアイソレーション構造を形成する方法
JP2007001007A Expired - Fee Related JP4168073B2 (ja) 1995-04-04 2007-01-09 集積回路においてトレンチアイソレーション構造を形成する方法

Family Applications After (1)

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JP2007001007A Expired - Fee Related JP4168073B2 (ja) 1995-04-04 2007-01-09 集積回路においてトレンチアイソレーション構造を形成する方法

Country Status (6)

Country Link
US (1) US5786263A (enExample)
EP (1) EP0736897B1 (enExample)
JP (2) JP4416843B2 (enExample)
KR (1) KR100394517B1 (enExample)
DE (1) DE69623679T2 (enExample)
TW (1) TW348274B (enExample)

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Also Published As

Publication number Publication date
DE69623679D1 (de) 2002-10-24
JP4168073B2 (ja) 2008-10-22
EP0736897A2 (en) 1996-10-09
JPH08279552A (ja) 1996-10-22
TW348274B (en) 1998-12-21
KR960036914A (ko) 1996-11-19
EP0736897A3 (en) 1998-03-11
US5786263A (en) 1998-07-28
JP2007096353A (ja) 2007-04-12
DE69623679T2 (de) 2003-05-22
EP0736897B1 (en) 2002-09-18
KR100394517B1 (ko) 2003-10-17

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