JP4394430B2 - 半導体素子の金属配線の形成方法 - Google Patents
半導体素子の金属配線の形成方法 Download PDFInfo
- Publication number
- JP4394430B2 JP4394430B2 JP2003411498A JP2003411498A JP4394430B2 JP 4394430 B2 JP4394430 B2 JP 4394430B2 JP 2003411498 A JP2003411498 A JP 2003411498A JP 2003411498 A JP2003411498 A JP 2003411498A JP 4394430 B2 JP4394430 B2 JP 4394430B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal wiring
- etching
- forming
- photoresist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02052—Wet cleaning only
Description
12 銅金属配線
14 第1エッチング停止膜
16 第2層間絶縁膜
18 第1BARC膜
20 第2エッチング停止膜
22 第3層間絶縁膜
24 第2BARC膜
Claims (4)
- 金属配線が埋め込まれた第1層間絶縁膜の上部に第1エッチング停止膜、第2層間絶縁膜、第2エッチング停止膜及び第3層間絶縁膜を順次形成する段階と、
前記第3層間絶縁膜の所定の領域に、ビアホールを定義する第1フォトレジストパターンを形成する段階と、
前記第1フォトレジストパターンをエッチングマスクとして第1エッチング停止膜までエッチングしてビアホールを形成した後、前記第1フォトレジストパターンを除去する段階と、
前記段階を経た結果物上にBARC膜を形成し、前記BARC膜の他の所定領域に、金属配線トレンチを定義する第2フォトレジストパターンを形成する段階と、
前記第2フォトレジストパターンをエッチングマスクとして第2エッチング停止膜までエッチングして金属配線トレンチを形成した後、前記第2フォトレジストパターン及びBARC膜を第1ウェットエッチング工程によって除去する段階と、
前記第2層間絶縁膜をエッチングマスクとして第1エッチング停止膜を第2ウェットエッチング工程によってエッチングする段階と、
前記段階を経た結果物の全面を第3ウェットエッチング工程によって洗浄する段階とを含む半導体素子の金属配線形成方法。 - 前記第1ウェットエッチング工程は、硫酸H2SO4と過水H2O2が2:1、4:1または6:1の割合で混合された水溶液を用いて100〜140℃程度のバス温度で2〜10分間行うことを特徴とする請求項1記載の半導体素子の金属配線形成方法。
- 前記第2ウェットエッチング工程は、HNO3が60〜90%混合された水溶液を用いて140〜180℃程度のバス温度で10〜60分間行うことを特徴とする請求項1記載の半導体素子の金属配線形成方法。
- 前記第3ウェットエッチング工程は、HFとDIウォータが200:1、19:1、500:1または600:1の割合で混合されたエッチング液を用いて常温のバス温度で10〜60分間行うことを特徴とする請求項1記載の半導体素子の金属配線形成方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020030049469A KR100542388B1 (ko) | 2003-07-18 | 2003-07-18 | 반도체 소자의 금속배선 형성방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005039180A JP2005039180A (ja) | 2005-02-10 |
JP4394430B2 true JP4394430B2 (ja) | 2010-01-06 |
Family
ID=34056915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003411498A Expired - Fee Related JP4394430B2 (ja) | 2003-07-18 | 2003-12-10 | 半導体素子の金属配線の形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7037822B2 (ja) |
JP (1) | JP4394430B2 (ja) |
KR (1) | KR100542388B1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100521050B1 (ko) * | 2003-12-30 | 2005-10-11 | 매그나칩 반도체 유한회사 | 반도체 소자의 금속 배선 형성 방법 |
KR100652062B1 (ko) | 2005-06-30 | 2006-12-01 | 엘지.필립스 엘시디 주식회사 | 인쇄판의 제조방법 |
US20070048991A1 (en) * | 2005-08-23 | 2007-03-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Copper interconnect structures and fabrication method thereof |
US20070218681A1 (en) * | 2006-03-16 | 2007-09-20 | Tokyo Electron Limited | Plasma etching method and computer-readable storage medium |
KR100871751B1 (ko) * | 2007-08-16 | 2008-12-05 | 주식회사 동부하이텍 | 이중 패터닝을 이용한 미세 패턴 형성방법 |
DE102007052048A1 (de) * | 2007-10-31 | 2009-05-14 | Advanced Micro Devices, Inc., Sunnyvale | Doppelintegrationsschema für Metallschicht mit geringem Widerstand |
KR20090068730A (ko) * | 2007-12-24 | 2009-06-29 | 주식회사 동부하이텍 | 반도체 소자 및 그의 제조 방법 |
JP2013030582A (ja) | 2011-07-28 | 2013-02-07 | Elpida Memory Inc | 半導体装置の製造方法 |
CN103515222A (zh) * | 2012-06-25 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | 顶层金属层沟槽的刻蚀方法 |
JP6131689B2 (ja) * | 2013-04-16 | 2017-05-24 | 住友電気工業株式会社 | 炭化珪素半導体装置の製造方法 |
US20180013998A1 (en) * | 2015-01-30 | 2018-01-11 | Ent. Services Development Corporation Lp | Relationship preserving projection of digital objects |
CN106128939B (zh) * | 2016-08-01 | 2018-10-26 | 上海华虹宏力半导体制造有限公司 | 处理异常mim电容介质层的方法 |
CN111128865A (zh) * | 2019-12-18 | 2020-05-08 | 华虹半导体(无锡)有限公司 | 大马士革互连制程工艺 |
US11854868B2 (en) * | 2021-03-30 | 2023-12-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Scalable patterning through layer expansion process and resulting structures |
CN113113295B (zh) * | 2021-04-06 | 2023-03-28 | 中山大学 | 一种片上硫系材料填充结构的制备方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6071814A (en) * | 1998-09-28 | 2000-06-06 | Taiwan Semiconductor Manufacturing Company | Selective electroplating of copper for damascene process |
US6323121B1 (en) * | 2000-05-12 | 2001-11-27 | Taiwan Semiconductor Manufacturing Company | Fully dry post-via-etch cleaning method for a damascene process |
TW447021B (en) * | 2000-06-19 | 2001-07-21 | United Microelectronics Corp | Method for preventing photoresist residue in a dual damascene process |
US6319809B1 (en) * | 2000-07-12 | 2001-11-20 | Taiwan Semiconductor Manfacturing Company | Method to reduce via poison in low-k Cu dual damascene by UV-treatment |
KR100443084B1 (ko) * | 2001-09-21 | 2004-08-04 | 삼성전자주식회사 | 구리 금속막의 연마 방법, 연마장치 및 구리 금속 배선형성 방법 |
US7109119B2 (en) * | 2002-10-31 | 2006-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
US7119006B2 (en) * | 2002-11-26 | 2006-10-10 | Texas Instruments Incorporated | Via formation for damascene metal conductors in an integrated circuit |
US7214609B2 (en) * | 2002-12-05 | 2007-05-08 | Texas Instruments Incorporated | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities |
-
2003
- 2003-07-18 KR KR1020030049469A patent/KR100542388B1/ko not_active IP Right Cessation
- 2003-12-10 JP JP2003411498A patent/JP4394430B2/ja not_active Expired - Fee Related
- 2003-12-10 US US10/731,480 patent/US7037822B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20050014384A1 (en) | 2005-01-20 |
KR100542388B1 (ko) | 2006-01-11 |
JP2005039180A (ja) | 2005-02-10 |
US7037822B2 (en) | 2006-05-02 |
KR20050009941A (ko) | 2005-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4394430B2 (ja) | 半導体素子の金属配線の形成方法 | |
KR101082993B1 (ko) | 레지스트용 박리제조성물 및 반도체장치의 제조방법 | |
TW200536052A (en) | Process for removing organic materials during formation of a metal interconnect | |
JPH05218017A (ja) | 半導体装置の製造方法 | |
TWI343078B (en) | Wet cleaning process and method for fabricating semiconductor device using the same | |
JP2005150681A (ja) | 半導体素子の金属配線形成方法 | |
JP2010056112A (ja) | 半導体装置の製造方法 | |
KR100650902B1 (ko) | 반도체 금속 배선 및 그 제조방법 | |
US6998347B2 (en) | Method of reworking layers over substrate | |
KR100571406B1 (ko) | 반도체 소자의 금속배선 제조 방법 | |
JP2678049B2 (ja) | 半導体装置の洗浄方法 | |
JPH04164330A (ja) | 半導体装置の製造方法 | |
KR100192173B1 (ko) | 반도체 소자의 텅스텐 플러그 형성방법 | |
KR100568098B1 (ko) | 금속 패턴 형성 방법 | |
KR100945871B1 (ko) | 듀얼 다마신 공정을 이용한 금속 배선 형성 방법 | |
KR100727438B1 (ko) | 디엘씨 유기절연막을 이용한 금속배선 형성 방법 | |
JP2003124310A (ja) | 半導体装置の製造方法 | |
JPH0536684A (ja) | 半導体装置の製造方法 | |
JP2005026482A (ja) | 半導体装置及びその製造方法 | |
JPH1092934A (ja) | 半導体素子の金属層間絶縁膜形成方法 | |
JP2004356474A (ja) | 半導体装置の製造方法 | |
KR19980048593A (ko) | 비아홀 세정 방법 | |
JP2004095813A (ja) | 配線構造の形成方法 | |
KR20050001536A (ko) | 플래쉬 메모리 소자의 금속배선 형성방법 | |
KR20050101609A (ko) | 반도체 소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060201 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20060904 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20061010 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20061130 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20090129 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090204 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20090219 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090428 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090915 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20091015 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121023 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131023 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |