KR100521050B1 - 반도체 소자의 금속 배선 형성 방법 - Google Patents
반도체 소자의 금속 배선 형성 방법 Download PDFInfo
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- KR100521050B1 KR100521050B1 KR10-2003-0100163A KR20030100163A KR100521050B1 KR 100521050 B1 KR100521050 B1 KR 100521050B1 KR 20030100163 A KR20030100163 A KR 20030100163A KR 100521050 B1 KR100521050 B1 KR 100521050B1
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- Prior art keywords
- metal
- forming
- metal wiring
- seed layer
- trench
- Prior art date
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- 239000002184 metal Substances 0.000 title claims abstract description 111
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 111
- 238000000034 method Methods 0.000 title claims abstract description 69
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 230000009977 dual effect Effects 0.000 claims abstract description 25
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 238000007517 polishing process Methods 0.000 claims description 21
- 239000000126 substance Substances 0.000 claims description 21
- 238000005260 corrosion Methods 0.000 claims description 19
- 230000007797 corrosion Effects 0.000 claims description 19
- 239000003112 inhibitor Substances 0.000 claims description 19
- 239000007800 oxidant agent Substances 0.000 claims description 16
- 239000002002 slurry Substances 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 14
- 238000005498 polishing Methods 0.000 claims description 13
- QRUDEWIWKLJBPS-UHFFFAOYSA-N benzotriazole Chemical compound C1=CC=C2N[N][N]C2=C1 QRUDEWIWKLJBPS-UHFFFAOYSA-N 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- OKKJLVBELUTLKV-UHFFFAOYSA-N Methanol Chemical compound OC OKKJLVBELUTLKV-UHFFFAOYSA-N 0.000 claims description 9
- BJEPYKJPYRNKOW-UHFFFAOYSA-N malic acid Chemical compound OC(=O)C(O)CC(O)=O BJEPYKJPYRNKOW-UHFFFAOYSA-N 0.000 claims description 6
- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 239000012964 benzotriazole Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- BJEPYKJPYRNKOW-REOHCLBHSA-N (S)-malic acid Chemical compound OC(=O)[C@@H](O)CC(O)=O BJEPYKJPYRNKOW-REOHCLBHSA-N 0.000 claims description 3
- 235000011090 malic acid Nutrition 0.000 claims description 3
- 239000001630 malic acid Substances 0.000 claims description 3
- 239000003755 preservative agent Substances 0.000 claims description 3
- 230000002335 preservative effect Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 5
- 238000007747 plating Methods 0.000 abstract description 6
- 239000007769 metal material Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 55
- 230000004888 barrier function Effects 0.000 description 8
- 239000011229 interlayer Substances 0.000 description 6
- -1 and H 2 O 2 Substances 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (14)
- 비아홀과 트렌치로 이루어진 듀얼 다마신 패턴이 형성된 반도체 기판이 제공되는 단계;상기 트렌치의 저면과, 상기 비아홀의 측벽 및 저면에 금속 시드층을 형성하는 단계;전기 도금법으로 상기 듀얼 다마신 패턴 내부에 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.
- 반도체 기판 상에 감광막을 형성하는 단계;트렌치 마스크를 이용한 1차 노광 공정으로 트렌치가 형성될 영역의 감광막을 소정 깊이까지 사다리꼴 형태로 변화시키는 단계;비아홀 마스크를 이용한 2차 노광 공정으로 비아홀이 형성될 영역의 감광막을 변화시키는 단계;상기 노광 공정들에 의해 변화된 감광막을 제거하는 단계;금속 시드층을 형성하되, 상기 트렌치의 측벽에는 상기 금속 시드층이 형성되지 않도록 상기 금속 시드층을 물리 기상 증착법으로 형성하는 단계;상기 감광막 상부에 형성된 상기 금속 시드층을 제거하는 단계; 및전기 도금법으로 상기 듀얼 다마신 패턴 내부에 금속 배선을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.
- 제 1 항 또는 제 2 항에 있어서,상기 금속 배선이 구리로 형성되는 반도체 소자의 금속 배선 형성 방법.
- 제 2 항에 있어서,상기 1차 노광 공정은 렌즈로부터 투과된 빛이 상기 감광막에 디포커싱 되도록 하여 상기 감광막을 소정 깊이까지 사다리꼴 형태로 변화시키는 반도체 소자의 금속 배선 형성 방법.
- 제 2 항에 있어서,상기 감광막 상부의 상기 금속 시드층은 화학적 기계적 연마 공정으로 제거되는 반도체 소자의 금속 배선 형성 방법.
- 제 5 항에 있어서,상기 화학적 기계적 연마 공정 시 연마제가 0wt% 내지 5wt% 포함된 슬러리가 공급되는 반도체 소자의 금속 배선 형성 방법.
- 제 6 항에 있어서,상기 슬러리에 DL_말산, 메탄올, 벤조트리아졸 또는 사과산이 포함된 반도체 소자의 금속 배선 형성 방법.
- 제 5 항에 있어서,상기 화학적 기계적 연마 공정의 연마율을 산화제 또는 부식방지제로 조절하는 반도체 소자의 금속 배선 형성 방법.
- 제 8 항에 있어서, 상기 부식 방지제를 사용하여 연마율을 조절하는 화학적 기계적 연마 공정은,상기 부식방지제를 10초 내지 3분 동안 패드에 공급하여 상기 금속 시드층의 표면과 접촉시키는 단계;상기 화학적 기계적 연마 공정을 실시하는 중간에 상기 슬러리의 공급을 중단하고, 부식방지제를 10초 내지 3분 동안 공급하는 단계; 및상기 화학적 기계적 연마 공정을 완료한 후, 부식방지제를 10초 내지 3분 동안 공급하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.
- 제 8 항 또는 제 9 항에 있어서,상기 부식 방지제가 BTA인 반도체 소자의 금속 배선 형성 방법.
- 제 8 항 또는 제 9 항에 있어서,상기 부식방지제의 농도가 0.01wt% 내지 1wt%인 반도체 소자의 금속 배선 형성 방법.
- 제 8 항에 있어서, 상기 산화제를 사용하여 연마율을 조절하는 화학적 기계적 연마 공정은,상기 슬러리와 혼합되는 상기 산화제의 혼합비가 1wt% 내지 50wt%인 반도체 소자의 금속 배선 형성 방법.
- 제 8 항 또는 제 12 항에 있어서,상기 산화제가 H2O2, Fe(NO3)3, KIO2, H5IO 6 인 반도체 소자의 금속 배선 형성 방법.
- 제 2 항에 있어서, 상기 금속 배선을 형성한 후,상기 감광막을 제거하는 단계; 및상기 금속 배선을 포함한 전체 구조 상에 절연막을 형성하는 단계를 더 포함하는 반도체 소자의 금속 배선 형성 방법.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0100163A KR100521050B1 (ko) | 2003-12-30 | 2003-12-30 | 반도체 소자의 금속 배선 형성 방법 |
US10/876,725 US20050142857A1 (en) | 2003-12-30 | 2004-06-28 | Method for forming metal line in semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0100163A KR100521050B1 (ko) | 2003-12-30 | 2003-12-30 | 반도체 소자의 금속 배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20050068579A KR20050068579A (ko) | 2005-07-05 |
KR100521050B1 true KR100521050B1 (ko) | 2005-10-11 |
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Application Number | Title | Priority Date | Filing Date |
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KR10-2003-0100163A KR100521050B1 (ko) | 2003-12-30 | 2003-12-30 | 반도체 소자의 금속 배선 형성 방법 |
Country Status (2)
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US (1) | US20050142857A1 (ko) |
KR (1) | KR100521050B1 (ko) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI349358B (en) * | 2007-06-08 | 2011-09-21 | Advanced Semiconductor Eng | Device having high aspect ratio via in low dielectric material and method for manufacturing the same |
CN103094196B (zh) * | 2011-11-02 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | 互连结构及其制造方法 |
CN103094197B (zh) * | 2011-11-02 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | 互连结构制造方法 |
US9373586B2 (en) | 2012-11-14 | 2016-06-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Copper etching integration scheme |
US9343399B2 (en) | 2013-07-12 | 2016-05-17 | Qualcomm Incorporated | Thick conductive stack plating process with fine critical dimension feature size for compact passive on glass technology |
CN104900582A (zh) * | 2014-03-06 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体结构及其制作方法 |
US9406629B2 (en) * | 2014-10-15 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor package structure and manufacturing method thereof |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH10125637A (ja) * | 1996-10-15 | 1998-05-15 | Toshiba Corp | 半導体装置の製造方法 |
JP3209169B2 (ja) * | 1997-11-28 | 2001-09-17 | 日本電気株式会社 | ゲート電極の形成方法 |
KR100280106B1 (ko) * | 1998-04-16 | 2001-03-02 | 윤종용 | 트렌치 격리 형성 방법 |
KR100350811B1 (ko) * | 2000-08-19 | 2002-09-05 | 삼성전자 주식회사 | 반도체 장치의 금속 비아 콘택 및 그 형성방법 |
US6897120B2 (en) * | 2001-01-03 | 2005-05-24 | Micron Technology, Inc. | Method of forming integrated circuitry and method of forming shallow trench isolation in a semiconductor substrate |
US6540935B2 (en) * | 2001-04-05 | 2003-04-01 | Samsung Electronics Co., Ltd. | Chemical/mechanical polishing slurry, and chemical mechanical polishing process and shallow trench isolation process employing the same |
US6569778B2 (en) * | 2001-06-28 | 2003-05-27 | Hynix Semiconductor Inc. | Method for forming fine pattern in semiconductor device |
US6736701B1 (en) * | 2001-11-20 | 2004-05-18 | Taiwan Semiconductor Manufacturing Company | Eliminate broken line damage of copper after CMP |
US6875692B1 (en) * | 2002-07-09 | 2005-04-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper electromigration inhibition by copper alloy formation |
KR100482179B1 (ko) * | 2002-12-16 | 2005-04-14 | 동부아남반도체 주식회사 | 반도체 소자 제조방법 |
US7201784B2 (en) * | 2003-06-30 | 2007-04-10 | Intel Corporation | Surfactant slurry additives to improve erosion, dishing, and defects during chemical mechanical polishing of copper damascene with low k dielectrics |
KR100542388B1 (ko) * | 2003-07-18 | 2006-01-11 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성방법 |
US6936534B2 (en) * | 2003-09-17 | 2005-08-30 | Micron Technology, Inc. | Method for the post-etch cleaning of multi-level damascene structures having underlying copper metallization |
US6911399B2 (en) * | 2003-09-19 | 2005-06-28 | Applied Materials, Inc. | Method of controlling critical dimension microloading of photoresist trimming process by selective sidewall polymer deposition |
-
2003
- 2003-12-30 KR KR10-2003-0100163A patent/KR100521050B1/ko active IP Right Grant
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2004
- 2004-06-28 US US10/876,725 patent/US20050142857A1/en not_active Abandoned
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Publication number | Publication date |
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US20050142857A1 (en) | 2005-06-30 |
KR20050068579A (ko) | 2005-07-05 |
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