JP4387865B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4387865B2 JP4387865B2 JP2004145584A JP2004145584A JP4387865B2 JP 4387865 B2 JP4387865 B2 JP 4387865B2 JP 2004145584 A JP2004145584 A JP 2004145584A JP 2004145584 A JP2004145584 A JP 2004145584A JP 4387865 B2 JP4387865 B2 JP 4387865B2
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- 239000004065 semiconductor Substances 0.000 title claims description 72
- 239000000758 substrate Substances 0.000 claims description 85
- 239000012535 impurity Substances 0.000 claims description 58
- 238000004519 manufacturing process Methods 0.000 description 56
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 55
- 229910052710 silicon Inorganic materials 0.000 description 55
- 239000010703 silicon Substances 0.000 description 55
- 230000003071 parasitic effect Effects 0.000 description 36
- 238000000034 method Methods 0.000 description 34
- 238000005468 ion implantation Methods 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 19
- 238000009826 distribution Methods 0.000 description 15
- 230000015556 catabolic process Effects 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000012299 nitrogen atmosphere Substances 0.000 description 6
- 238000005215 recombination Methods 0.000 description 6
- 230000006798 recombination Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000012298 atmosphere Substances 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000001590 oxidative effect Effects 0.000 description 4
- 230000001172 regenerating effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
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- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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Description
まず、図14Aに示されるように、P型シリコン基板501上にN型埋め込み層502及びN型エピタキシャル層503を順次形成する。このとき、N型埋め込み層502は、N型エピタキシャル層503よりも濃度が濃くなるように形成され、このN型埋め込み層502及びN型エピタキシャル層503がDMOSトランジスタのドレイン504となる。
これによって、半導体装置がオンしたとき低抵抗体である埋め込み層を伝い電流が流れるので、オン抵抗の低い半導体装置を実現することができる。
これによって、LOCOS酸化膜形成のための高温での熱処理により、埋め込み層は広範囲に拡散し、埋め込み層内での正孔の再結合が多く行われるので、寄生PNPトランジスタのhfeを更に小さくする半導体装置を実現することができる。
これによって、ボディー層下端が埋め込み層とのみ接するようにすることができるので、ボディー層下端における不純物濃度を低くすることができ、ボディー層下端における接合耐圧を向上させることができる。従って、ブレークダウン電圧を向上させる半導体装置を実現することができる。
また、前記ウェル層の深さは、前記ウェル層の上方に位置する前記第1のゲート電極あるいは前記第2のゲート電極の長さよりも浅くてもよいし、前記ウェル層の深さは、前記ウェル層の上方に位置する前記ゲート電極の長さよりも浅くてもよい。
また、前記半導体装置の製造方法は、さらに、前記半導体基板上にLOCOS酸化膜を形成するLOCOS酸化膜形成工程を含み、前記LOCOS酸化膜形成工程は、前記埋め込み層形成工程の後におこなわれてもよい。
また、前記LOCOS酸化膜形成工程、前記埋め込み層形成工程及び前記ボディー層形成工程において、前記埋め込み層の上端が前記ボディー層の下端と実質的に接するように前記埋め込み層及び前記ボディー層を形成してもよいし、前記埋め込み層形成工程において、前記埋め込み層の不純物濃度が前記ウェル層の不純物濃度よりも高くなるように前記埋め込み層を形成してもよい。
また、前記ボディー層形成工程において、前記半導体基板の前記ウェル層が形成されていない部分にボディー層を形成してもよい。
また、前記ゲート電極は、所定の間隔を有して前記半導体基板上に形成された第1のゲート電極と第2のゲート電極とからなり、前記ウェル層形成工程において、前記第1のゲート電極及び前記第2のゲート電極をマスクとしたセルフアラインで前記ウェル層を形成してもよいし、前記LOCOS酸化膜は、所定の間隔を有して前記半導体基板上に形成された第1のLOCOS酸化膜と、前記第2のLOCOS酸化膜とからなり、前記ゲート電極は、前記第1のLOCOS酸化膜及び前記半導体基板にまたがって前記第1のLOCOS酸化膜及び前記半導体基板上に形成され、前記ウェル層形成工程において、前記第1のLOCOS酸化膜及び前記第2のLOCOS酸化膜をマスクとしたセルフアラインで前記ウェル層を形成し、前記ボディー層形成工程において、前記半導体基板の前記ウェル層が形成されていない部分にボディー層を形成してもよい。
これによって、安定した特性を有する半導体装置の製造方法を実現することができる。
これによって、良好な周波数特性を有する半導体装置の製造方法を実現することができる。
(第1の実施の形態)
図1は、本発明の第1の実施の形態のDMOSトランジスタの断面図である。
N型埋め込み層3は、P型ボディー層6下方に位置し、N型埋め込み層3上端は、P型ボディー層6下端と実質的に接している。すなわち、N型埋め込み層3上端は、P型ボディー層6下端と接しているか、あるいはP型ボディー層6と重ならない方向にP型ボディー層6下端と離れていても、大きく離れずに、例えば0.1μm〜0.2μmの間隔を持って近接している。N型埋め込み層3の不純物濃度は、N型ウェル層2の不純物濃度よりも高い、つまりN型埋め込み層3の不純物濃度のピークは、N型ウェル層2表面の不純物濃度より高い。
まず、図2Aに示されるように、イオン注入法でN型不純物を注入し、高温での熱処理をおこなってP型シリコン基板1内にN型ウェル層2を形成する。
上記第1の実施の形態のDMOSトランジスタにおいて、P型ボディー層はN型ウェル層内に形成され、P型ボディー層下端はN型埋め込み層上端と実質的に接するので、P型ボディー層下端はN型ウェル層及びN型埋め込み層と接する。よって、図5のDMOSトランジスタの不純物分布(図1のY1−Y1’部における不純物分布)に示されるように、P型ボディー層下端における不純物濃度は8×1016/cm3程度と高くなるので、P型ボディー層下端における接合耐圧が低下する。そこで、第2の実施の形態のDMOSトランジスタは、ブレークダウン電圧を向上させるDMOSトランジスタを実現することを目的とする。以下、第1の実施の形態と異なる点を中心に説明する。
本実施の形態のDMOSトランジスタは、N型ウェル層102、N型埋め込み層103及びP型ボディー層105が内部に形成されたP型シリコン基板101と、酸化膜及びポリシリコン等の配線材料からなるゲート電極104と、LOCOS酸化膜(図外)とから構成される。このとき、N型ウェル層102及びN型埋め込み層103がDMOSトランジスタのドレインとなる。
N型埋め込み層103は、P型ボディー層105下方に位置し、N型埋め込み層103上端は、P型ボディー層105下端と実質的に接している。すなわち、N型埋め込み層103上端は、P型ボディー層105下端と接しているか、あるいはP型ボディー層105と重ならない方向にP型ボディー層105下端と離れていても、大きく離れずに、例えば0.1μm〜0.2μmの間隔を持って近接している。N型埋め込み層103の不純物濃度は、N型ウェル層102の不純物濃度よりも高い、つまりN型埋め込み層103の不純物濃度のピークは、N型ウェル層102表面の不純物濃度より高い。
まず、図7Aに示されるように、イオン注入法でN型不純物を注入し、高温での熱処理をおこなってP型シリコン基板101内にN型ウェル層102を形成する。このとき、N型ウェル層102はP型ボディー層105が形成される部分に形成されないように離間して形成される。
上記第2の実施の形態のDMOSトランジスタにおいて、N型ウェル層はP型ボディー層の両側に離間して位置する2つの層からなる。よって、N型ウェル層とP型ボディー層との間の距離が製造ばらつきにより変動するので、DMOSトランジスタの特性が安定しない。例えば、N型ウェル層とP型ボディー層とが重なると、重なる部分でP型ボディー層の不純物濃度が薄くなり、ゲート閾値電圧あるいは耐圧等が変化する。そこで、第3の実施の形態のDMOSトランジスタは、安定した特性を有するDMOSトランジスタを実現することを目的とする。以下、第2の実施の形態と異なる点を中心に説明する。
本実施の形態のDMOSトランジスタは、N型ウェル層202、N型埋め込み層203及びP型ボディー層205が内部に形成されたP型シリコン基板201と、酸化膜及びポリシリコン等の配線材料からなるゲート電極204と、LOCOS酸化膜(図外)とから構成される。このとき、N型ウェル層202及びN型埋め込み層203がDMOSトランジスタのドレインとなる。
N型埋め込み層203は、P型ボディー層205下方に位置し、N型埋め込み層203上端は、P型ボディー層205下端と実質的に接している。すなわち、N型埋め込み層203上端は、P型ボディー層205下端と接しているか、あるいはP型ボディー層205と重ならない方向にP型ボディー層205下端と離れていても、大きく離れずに、例えば0.1μm〜0.2μmの間隔を持って近接している。N型埋め込み層203の不純物濃度は、N型ウェル層202の不純物濃度よりも高い、つまりN型埋め込み層203の不純物濃度のピークは、N型ウェル層202表面の不純物濃度より高い。
次に、以上のような構造を有するDMOSトランジスタの製造方法について図10A〜図10Dに示す断面図に沿って説明する。
図11は、本発明の第4の実施の形態のDMOSトランジスタの断面図である。
N型埋め込み層302は、P型ボディー層306下方に位置し、N型埋め込み層302上端は、P型ボディー層306下端と実質的に接している。すなわち、N型埋め込み層302上端は、P型ボディー層306下端と接しているか、あるいはP型ボディー層306と重ならない方向にP型ボディー層306下端と離れていても、大きく離れずに、例えば0.1μm〜0.2μmの間隔を持って近接している。N型埋め込み層302の不純物濃度は、N型ウェル層304の不純物濃度よりも高い、つまりN型埋め込み層302の不純物濃度のピークは、N型ウェル層304表面の不純物濃度より高い。
ゲート電極305は、P型シリコン基板301及びLOCOS酸化膜303にまたがってLOCOS酸化膜303及びP型シリコン基板301上に形成される。
まず、図12Aに示されるように、イオン注入法でN型不純物を高エネルギー注入し、イオン注入によるダメージ回復のため、例えば窒素雰囲気で900℃、30分程度の熱処理を行う。P型シリコン基板301内にN型埋め込み層302を形成した後、P型シリコン基板301上にLOCOS酸化膜303を形成する。LOCOS酸化膜303の形成に際しては、例えば、酸化雰囲気で1000℃、100分の熱処理が行われるため、N型埋め込み層302は拡散され、P型シリコン基板301の表面側に広げられる。なお、N型埋め込み層302の形成方法は、第1の実施の形態のDMOSトランジスタにおけるものと同様のため、説明は省略する。
次に、図12Dに示されるように、ゲート電極305をマスクとしたセルフアラインにより、N型ウェル層304が形成されていないP型シリコン基板301内にP型ボディー層306を形成し、このP型ボディー層306内にN型ソース層307を形成する。そして、ゲート電極305から離れたN型ウェル層304内にN型ドレインコンタクト層308を形成する。さらに、イオン注入によるダメージ回復のため、例えば窒素雰囲気で900℃、30分程度の熱処理を行う。このとき、P型ボディー層306両端がN型ウェル層304に届くように、P型ボディー層306の形成条件を設定する。
2、102、202、304、600 N型ウェル層
3、103、203、302、502、610 N型埋め込み層
4、303 LOCOS酸化膜
5、104、204、305、505 ゲート電極
6、105、205、306、506 P型ボディー層
7、106、206、307、507 N型ソース層
8、107、207、308、508 N型ドレインコンタクト層
401 電源ライン
402 出力端子
403 第1のDMOSトランジスタ
404 制御回路
405 グランドライン
406 第2のDMOSトランジスタ
503 N型エピタキシャル層
504 ドレイン
Claims (3)
- 第1導電型の半導体基板と、
前記半導体基板上に形成されたゲート電極とを備え、
前記半導体基板は、
チャネル長方向に離間して形成された前記第1導電型とは反対極性の第2導電型の2つのウェル層と、
前記2つのウェル層の一方のウェル層内に形成された第2導電型のドレインコンタクト層と、
第1導電型のボディー層と、
前記ボディー層内に形成された第2導電型のソース層と、
前記ボディー層の下方に形成された第2導電型の埋め込み層とを有し、
前記ボディー層は前記2つのウェル層間に位置する前記第1導電型の半導体基板の領域に、前記2つのウェル層の両方に隣接して形成され、
前記ボディー層及び前記ソース層は、前記ゲート電極をマスクとしたセルフアラインで形成され、
前記ドレインコンタクト層は、前記ゲート電極下方のボディー層を挟んで前記ソース層と反対側に形成され、
前記埋め込み層の上端は、前記ボディー層の下端と接している
ことを特徴とする半導体装置。 - 前記埋め込み層の不純物濃度は、前記2つのウェル層の不純物濃度よりも高い
ことを特徴とする請求項1に記載の半導体装置。 - 前記ボディー層と前記ソース層とは電気的に接続されている
ことを特徴とする請求項1又は2に記載の半導体装置。
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US11/075,895 US7851883B2 (en) | 2004-05-14 | 2005-03-10 | Semiconductor device and method of manufacture thereof |
CNB200510070258XA CN100474622C (zh) | 2004-05-14 | 2005-05-13 | 半导体器件及其制造方法 |
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JP2013122948A (ja) * | 2011-12-09 | 2013-06-20 | Seiko Instruments Inc | 半導体装置およびその製造方法 |
CN103187435B (zh) * | 2011-12-28 | 2016-06-08 | 上海华虹宏力半导体制造有限公司 | 高压隔离n型ldmos器件及其制造方法 |
US8853022B2 (en) | 2012-01-17 | 2014-10-07 | Globalfoundries Singapore Pte. Ltd. | High voltage device |
US8822291B2 (en) * | 2012-01-17 | 2014-09-02 | Globalfoundries Singapore Pte. Ltd. | High voltage device |
KR101885942B1 (ko) * | 2014-11-19 | 2018-08-07 | 매그나칩 반도체 유한회사 | 반도체 소자 및 제조 방법 |
US11088031B2 (en) | 2014-11-19 | 2021-08-10 | Key Foundry Co., Ltd. | Semiconductor and method of fabricating the same |
KR101975630B1 (ko) * | 2015-04-03 | 2019-08-29 | 매그나칩 반도체 유한회사 | 접합 트랜지스터와 고전압 트랜지스터 구조를 포함한 반도체 소자 및 그 제조 방법 |
US10784372B2 (en) * | 2015-04-03 | 2020-09-22 | Magnachip Semiconductor, Ltd. | Semiconductor device with high voltage field effect transistor and junction field effect transistor |
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US5324982A (en) * | 1985-09-25 | 1994-06-28 | Hitachi, Ltd. | Semiconductor memory device having bipolar transistor and structure to avoid soft error |
JPS62217664A (ja) | 1986-03-19 | 1987-09-25 | Nissan Motor Co Ltd | 半導体装置 |
JP3057757B2 (ja) | 1990-11-29 | 2000-07-04 | 日産自動車株式会社 | トランジスタ |
JP2932112B2 (ja) | 1991-07-09 | 1999-08-09 | 株式会社日立製作所 | 核融合炉の運転操作支援装置 |
US5719421A (en) * | 1994-10-13 | 1998-02-17 | Texas Instruments Incorporated | DMOS transistor with low on-resistance and method of fabrication |
JP3372773B2 (ja) | 1995-09-08 | 2003-02-04 | 松下電器産業株式会社 | 半導体装置及びその製造方法 |
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KR100301071B1 (ko) * | 1998-10-26 | 2001-11-22 | 김덕중 | 디모스(dmos)트랜지스터및그제조방법 |
KR100284746B1 (ko) * | 1999-01-15 | 2001-03-15 | 김덕중 | 소스 영역 하부의 바디 저항이 감소된 전력용 디모스 트랜지스터 |
US6144069A (en) * | 1999-08-03 | 2000-11-07 | United Microelectronics Corp. | LDMOS transistor |
JP2003303961A (ja) | 2002-04-09 | 2003-10-24 | Sanyo Electric Co Ltd | Mos半導体装置 |
KR100867574B1 (ko) * | 2002-05-09 | 2008-11-10 | 페어차일드코리아반도체 주식회사 | 고전압 디바이스 및 그 제조방법 |
US6882023B2 (en) * | 2002-10-31 | 2005-04-19 | Motorola, Inc. | Floating resurf LDMOSFET and method of manufacturing same |
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CN1697197A (zh) | 2005-11-16 |
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