JP4352365B2 - 集積回路パッケージの製造方法および集積回路パッケージ - Google Patents

集積回路パッケージの製造方法および集積回路パッケージ Download PDF

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Publication number
JP4352365B2
JP4352365B2 JP2001218921A JP2001218921A JP4352365B2 JP 4352365 B2 JP4352365 B2 JP 4352365B2 JP 2001218921 A JP2001218921 A JP 2001218921A JP 2001218921 A JP2001218921 A JP 2001218921A JP 4352365 B2 JP4352365 B2 JP 4352365B2
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integrated circuit
conductive layer
circuit package
region
conductive
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Japanese (ja)
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JP2002093949A5 (OSRAM
JP2002093949A (ja
Inventor
コーン チャールズ
アール ホーク，ジュニヤ ドナルド
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Agere Systems LLC
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Agere Systems LLC
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2001218921A 2000-07-21 2001-07-19 集積回路パッケージの製造方法および集積回路パッケージ Expired - Lifetime JP4352365B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/620939 2000-07-21
US09/620,939 US6465882B1 (en) 2000-07-21 2000-07-21 Integrated circuit package having partially exposed conductive layer

Related Child Applications (1)

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JP2008045768A Division JP5135493B2 (ja) 2000-07-21 2008-02-27 集積回路パッケージ

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JP2002093949A JP2002093949A (ja) 2002-03-29
JP2002093949A5 JP2002093949A5 (OSRAM) 2004-09-09
JP4352365B2 true JP4352365B2 (ja) 2009-10-28

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JP2008045768A Expired - Lifetime JP5135493B2 (ja) 2000-07-21 2008-02-27 集積回路パッケージ

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US (1) US6465882B1 (OSRAM)
JP (2) JP4352365B2 (OSRAM)
KR (1) KR100678878B1 (OSRAM)
GB (1) GB2370413B (OSRAM)
TW (1) TW512503B (OSRAM)

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US7088559B2 (en) * 2001-08-10 2006-08-08 Seagate Technology Llc Integrated interconnect and method of manufacture therefor
DE10233607B4 (de) 2002-07-24 2005-09-29 Siemens Ag Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
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US20040183167A1 (en) * 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
US6956286B2 (en) * 2003-08-05 2005-10-18 International Business Machines Corporation Integrated circuit package with overlapping bond fingers
US7166905B1 (en) 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
TWI286917B (en) * 2005-01-14 2007-09-11 Au Optronics Corp Thermal bonding structure and manufacture process of flexible printed circuit (FPC)
TW200703606A (en) * 2005-07-15 2007-01-16 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US8447700B2 (en) 2005-10-11 2013-05-21 Amazon Technologies, Inc. Transaction authorization service
WO2010090075A1 (ja) * 2009-02-05 2010-08-12 アルプス電気株式会社 磁気検出装置
CN103000539B (zh) * 2012-11-16 2016-05-18 日月光半导体制造股份有限公司 半导体封装构造及其制造方法

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TW512503B (en) 2002-12-01
GB2370413A (en) 2002-06-26
JP5135493B2 (ja) 2013-02-06
US6465882B1 (en) 2002-10-15
KR20020008781A (ko) 2002-01-31
GB0117310D0 (en) 2001-09-05
JP2008172267A (ja) 2008-07-24
KR100678878B1 (ko) 2007-02-07
GB2370413B (en) 2004-10-20
JP2002093949A (ja) 2002-03-29

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