JP4322189B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

Info

Publication number
JP4322189B2
JP4322189B2 JP2004255531A JP2004255531A JP4322189B2 JP 4322189 B2 JP4322189 B2 JP 4322189B2 JP 2004255531 A JP2004255531 A JP 2004255531A JP 2004255531 A JP2004255531 A JP 2004255531A JP 4322189 B2 JP4322189 B2 JP 4322189B2
Authority
JP
Japan
Prior art keywords
film
semiconductor device
connection pad
silicon oxide
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004255531A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006073805A5 (https=
JP2006073805A (ja
Inventor
康弘 中
富生 岩▲崎▼
秀一 奥田
裕二 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2004255531A priority Critical patent/JP4322189B2/ja
Priority to US11/172,207 priority patent/US20060043605A1/en
Publication of JP2006073805A publication Critical patent/JP2006073805A/ja
Publication of JP2006073805A5 publication Critical patent/JP2006073805A5/ja
Priority to US12/401,491 priority patent/US20090174061A1/en
Application granted granted Critical
Publication of JP4322189B2 publication Critical patent/JP4322189B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/012Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251Changing the shapes of bumps
    • H10W72/01255Changing the shapes of bumps by using masks
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/071Connecting or disconnecting
    • H10W72/072Connecting or disconnecting of bump connectors
    • H10W72/07251Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/551Materials of bond wires
    • H10W72/552Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/921Structures or relative sizes of bond pads
    • H10W72/923Bond pads having multiple stacked layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2004255531A 2004-09-02 2004-09-02 半導体装置 Expired - Fee Related JP4322189B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2004255531A JP4322189B2 (ja) 2004-09-02 2004-09-02 半導体装置
US11/172,207 US20060043605A1 (en) 2004-09-02 2005-06-29 Semiconductor device
US12/401,491 US20090174061A1 (en) 2004-09-02 2009-03-10 Semiconductor Device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004255531A JP4322189B2 (ja) 2004-09-02 2004-09-02 半導体装置

Publications (3)

Publication Number Publication Date
JP2006073805A JP2006073805A (ja) 2006-03-16
JP2006073805A5 JP2006073805A5 (https=) 2006-11-24
JP4322189B2 true JP4322189B2 (ja) 2009-08-26

Family

ID=35941942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004255531A Expired - Fee Related JP4322189B2 (ja) 2004-09-02 2004-09-02 半導体装置

Country Status (2)

Country Link
US (2) US20060043605A1 (https=)
JP (1) JP4322189B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4322189B2 (ja) * 2004-09-02 2009-08-26 株式会社ルネサステクノロジ 半導体装置
JP5162851B2 (ja) * 2006-07-14 2013-03-13 富士通セミコンダクター株式会社 半導体装置及びその製造方法
DE102007023590A1 (de) * 2007-05-21 2008-11-27 Epcos Ag Bauelement mit mechanisch belastbarer Anschlussfläche
US7919409B2 (en) * 2008-08-15 2011-04-05 Air Products And Chemicals, Inc. Materials for adhesion enhancement of copper film on diffusion barriers
US8952553B2 (en) 2009-02-16 2015-02-10 Toyota Jidosha Kabushiki Kaisha Semiconductor device with stress relaxation during wire-bonding
WO2011033393A1 (en) * 2009-09-17 2011-03-24 Koninklijke Philips Electronics N.V. Geometry of contact sites at brittle inorganic layers in electronic devices
DE102012109161B4 (de) * 2012-09-27 2021-10-28 Pictiva Displays International Limited Organisches, optoelektronisches Bauelement, Verfahren zum Herstellen eines organischen, optoelektronischen Bauelementes und Verfahren zum stoffschlüssigen, elektrischen Kontaktieren
US9245770B2 (en) * 2012-12-20 2016-01-26 Stats Chippac, Ltd. Semiconductor device and method of simultaneous molding and thermalcompression bonding
JP7629756B2 (ja) * 2021-03-03 2025-02-14 Tdk株式会社 積層電極、電極付き歪抵抗膜および圧力センサ
DE112021008330T5 (de) * 2021-10-07 2024-08-29 Tdk Corporation Laminierte elektrode, mit elektroden ausgestatteter dehnungswiderstandsfilm und drucksensor

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6742248B2 (en) * 2001-05-14 2004-06-01 The Boeing Company Method of forming a soldered electrical connection
DE10308275A1 (de) * 2003-02-26 2004-09-16 Advanced Micro Devices, Inc., Sunnyvale Strahlungsresistentes Halbleiterbauteil
US20050104208A1 (en) * 2003-11-14 2005-05-19 International Business Machines Corporation Stabilizing copper overlayer for enhanced c4 interconnect reliability
US6951803B2 (en) * 2004-02-26 2005-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Method to prevent passivation layer peeling in a solder bump formation process
US7064446B2 (en) * 2004-03-29 2006-06-20 Intel Corporation Under bump metallization layer to enable use of high tin content solder bumps
JP4322189B2 (ja) * 2004-09-02 2009-08-26 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
US20060043605A1 (en) 2006-03-02
US20090174061A1 (en) 2009-07-09
JP2006073805A (ja) 2006-03-16

Similar Documents

Publication Publication Date Title
KR100532179B1 (ko) 집적 회로 패키지를 위한 칩 규모 볼 그리드 어레이
US20090174061A1 (en) Semiconductor Device
JP2008016818A (ja) 半導体装置およびその製造方法
US20250343199A1 (en) Electronic device and manufacturing method thereof
US20090201657A1 (en) Wiring substrate for use in semiconductor apparatus, method for fabricating the same, and semiconductor apparatus using the same
KR20080111397A (ko) 전자 장치의 제조 방법 및 전자 장치
US8349736B2 (en) Semiconductor device manufacturing method and semiconductor device
JP5279180B2 (ja) 半導体装置
JP3402086B2 (ja) 半導体装置およびその製造方法
JP3279470B2 (ja) 半導体装置およびその製造方法
JP3281591B2 (ja) 半導体装置およびその製造方法
JP2006210406A (ja) 配線とそれを備えた半導体装置
JP4506168B2 (ja) 半導体装置およびその実装構造
JP4638614B2 (ja) 半導体装置の作製方法
JP5165190B2 (ja) 半導体装置及びその製造方法
JP2004063804A (ja) 半導体装置、積層型半導体装置およびそれらの製造方法
JP3403689B2 (ja) 半導体装置
JP2021027122A (ja) 半導体装置
KR100813623B1 (ko) 가요성 필름, 이를 이용한 반도체 패키지 및 제조방법
JP3417292B2 (ja) 半導体装置
KR20100002870A (ko) 반도체 패키지의 제조 방법
JP3889311B2 (ja) プリント配線板
JP2007103614A (ja) 半導体装置および半導体装置の製造方法
JP4668608B2 (ja) 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
JP5036217B2 (ja) 半導体装置及びその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061004

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20061004

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20081112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081118

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090115

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090526

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090602

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120612

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120612

Year of fee payment: 3

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120612

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120612

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130612

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees