JP4294696B2 - 半導体装置の製造方法および製造装置、ならびに記憶媒体 - Google Patents

半導体装置の製造方法および製造装置、ならびに記憶媒体 Download PDF

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JP4294696B2
JP4294696B2 JP2007024212A JP2007024212A JP4294696B2 JP 4294696 B2 JP4294696 B2 JP 4294696B2 JP 2007024212 A JP2007024212 A JP 2007024212A JP 2007024212 A JP2007024212 A JP 2007024212A JP 4294696 B2 JP4294696 B2 JP 4294696B2
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Prior art keywords
chamber
gas
semiconductor device
manufacturing
nitriding
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Expired - Fee Related
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JP2007024212A
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Japanese (ja)
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JP2008192739A (ja
JP2008192739A5 (enExample
Inventor
卓司 佐古
勇作 柏木
宏至 戸島
薫 前川
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Priority to JP2007024212A priority Critical patent/JP4294696B2/ja
Priority to TW097100722A priority patent/TW200842977A/zh
Priority to US12/024,445 priority patent/US20080184543A1/en
Publication of JP2008192739A publication Critical patent/JP2008192739A/ja
Publication of JP2008192739A5 publication Critical patent/JP2008192739A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32192—Microwave generated discharge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
JP2007024212A 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体 Expired - Fee Related JP4294696B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007024212A JP4294696B2 (ja) 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体
TW097100722A TW200842977A (en) 2007-02-02 2008-01-08 Method and apparatus for manufacturing semiconductor device, and storage medium for executing the method
US12/024,445 US20080184543A1 (en) 2007-02-02 2008-02-01 Method and apparatus for manufacturing semiconductor device, and storage medium for executing the method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007024212A JP4294696B2 (ja) 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体

Publications (3)

Publication Number Publication Date
JP2008192739A JP2008192739A (ja) 2008-08-21
JP2008192739A5 JP2008192739A5 (enExample) 2008-10-16
JP4294696B2 true JP4294696B2 (ja) 2009-07-15

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JP2007024212A Expired - Fee Related JP4294696B2 (ja) 2007-02-02 2007-02-02 半導体装置の製造方法および製造装置、ならびに記憶媒体

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US (1) US20080184543A1 (enExample)
JP (1) JP4294696B2 (enExample)
TW (1) TW200842977A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8072075B2 (en) * 2006-09-04 2011-12-06 Nicolas Jourdan CuSiN/SiN diffusion barrier for copper in integrated-circuit devices
JP5781720B2 (ja) 2008-12-15 2015-09-24 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP5582727B2 (ja) 2009-01-19 2014-09-03 株式会社東芝 半導体装置の製造方法及び半導体装置
KR20120064966A (ko) * 2010-12-10 2012-06-20 에스케이하이닉스 주식회사 반도체 장치 제조 방법
US9330915B2 (en) * 2013-12-10 2016-05-03 Taiwan Semiconductor Manufacturing Co., Ltd. Surface pre-treatment for hard mask fabrication
US9385086B2 (en) 2013-12-10 2016-07-05 Taiwan Semiconductor Manufacturing Co., Ltd. Bi-layer hard mask for robust metallization profile
JP5856227B2 (ja) * 2014-05-26 2016-02-09 ルネサスエレクトロニクス株式会社 半導体装置
JP2016111104A (ja) * 2014-12-03 2016-06-20 株式会社Ｊｏｌｅｄ 薄膜半導体基板の製造方法
JP6593635B2 (ja) * 2014-12-24 2019-10-23 株式会社ジェイテクト 樹脂製部材の製造方法
KR20240041664A (ko) * 2022-09-23 2024-04-01 주식회사 에이치피에스피 반도체 소자의 제조 방법
JP2025099459A (ja) * 2023-12-21 2025-07-03 東京エレクトロン株式会社 基板処理方法及び基板処理装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000063956A1 (en) * 1999-04-20 2000-10-26 Sony Corporation Method and apparatus for thin-film deposition, and method of manufacturing thin-film semiconductor device
ATE418158T1 (de) * 1999-08-17 2009-01-15 Applied Materials Inc Oberflächenbehandlung von kohlenstoffdotierten sio2-filmen zur erhöhung der stabilität während der o2-veraschung
US6756239B1 (en) * 2003-04-15 2004-06-29 Hewlett-Packard Development Company, L.P. Method for constructing a magneto-resistive element
JP4516447B2 (ja) * 2005-02-24 2010-08-04 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4509864B2 (ja) * 2005-05-30 2010-07-21 東京エレクトロン株式会社 プラズマ処理方法およびプラズマ処理装置
DE102006056624B4 (de) * 2006-11-30 2012-03-29 Globalfoundries Inc. Verfahren zur Herstellung einer selbstjustierten CuSiN-Deckschicht in einem Mikrostrukturbauelement
US7718548B2 (en) * 2006-12-06 2010-05-18 Applied Materials, Inc. Selective copper-silicon-nitride layer formation for an improved dielectric film/copper line interface

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US20080184543A1 (en) 2008-08-07
TW200842977A (en) 2008-11-01
JP2008192739A (ja) 2008-08-21

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