JP4167565B2 - 部分soi基板の製造方法 - Google Patents
部分soi基板の製造方法 Download PDFInfo
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- JP4167565B2 JP4167565B2 JP2003283479A JP2003283479A JP4167565B2 JP 4167565 B2 JP4167565 B2 JP 4167565B2 JP 2003283479 A JP2003283479 A JP 2003283479A JP 2003283479 A JP2003283479 A JP 2003283479A JP 4167565 B2 JP4167565 B2 JP 4167565B2
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- Prior art keywords
- oxide film
- substrate
- region
- soi
- semiconductor substrate
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- 239000000758 substrate Substances 0.000 title claims description 131
- 238000000034 method Methods 0.000 title claims description 30
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 39
- 239000001301 oxygen Substances 0.000 claims description 39
- -1 oxygen ions Chemical class 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 37
- 238000005530 etching Methods 0.000 claims description 7
- 239000007789 gas Substances 0.000 claims description 4
- 239000010408 film Substances 0.000 description 105
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 50
- 229910052710 silicon Inorganic materials 0.000 description 50
- 239000010703 silicon Substances 0.000 description 50
- 230000007547 defect Effects 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 230000001133 acceleration Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 210000000746 body region Anatomy 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Description
前記半導体基板の露出領域の表面を等方性エッチングにより除去して凹部を形成し、前記マスクの端部を前記半導体基板上に突出させる工程と、
前記半導体基板に酸素イオンを注入する工程と、
前記半導体基板を加熱処理して、前記半導体基板の内部に、均一な膜厚の第1の埋め込み酸化膜と傾斜および曲率を有する不均一な厚さの第2の埋め込み酸化膜とからなる埋め込み酸化膜を形成するとともに、前記半導体基板の表面に熱酸化膜を形成する工程と、
前記半導体基板表面の前記熱酸化膜および前記マスクを除去する工程と
を具備することを特徴とする。
図2を参照して、本実施形態にかかる部分SOI基板の製造方法を説明する。
図7を参照して、本実施形態にかかる部分SOI基板の製造方法を説明する。
図9を参照して、本実施形態にかかる部分SOI基板の製造方法を説明する。
本発明の実施形態にかかる半導体装置における電気的特性を、以下のように評価した。
Claims (6)
- 半導体基板の所定の領域にマスクを形成する工程と、
前記半導体基板の露出領域の表面を等方性エッチングにより除去して凹部を形成し、前記マスクの端部を前記半導体基板上に突出させる工程と、
前記半導体基板に酸素イオンを注入する工程と、
前記半導体基板を加熱処理して、前記半導体基板の内部に、均一な膜厚の第1の埋め込み酸化膜と傾斜および曲率を有する不均一な厚さの第2の埋め込み酸化膜とからなる埋め込み酸化膜を形成するとともに、前記半導体基板の表面に熱酸化膜を形成する工程と、
前記半導体基板表面の前記熱酸化膜および前記マスクを除去する工程と
を具備することを特徴とする部分SOI基板の製造方法。 - 前記半導体基板の等方性エッチングは、ガスを用いて行なわれることを特徴とする請求項1に記載の部分SOI基板の製造方法。
- 前記ガスは塩酸ガスであることを特徴とする請求項2に記載の部分SOI基板の製造方法。
- 前記酸素イオンは、前記半導体基板の主面に対して垂直に注入されることを特徴とする請求項1ないし3のいずれか1項に記載の部分SOI基板の製造方法。
- 前記酸素イオンは、前記半導体基板の主面に対して斜めに注入されることを特徴とする請求項1ないし3のいずれか1項に記載の部分SOI基板の製造方法。
- 前記凹部は、0.1〜0.5μmの深さで前記半導体基板の表面に形成されることを特徴とする請求項1ないし5のいずれか1項に記載の部分SOI基板の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003283479A JP4167565B2 (ja) | 2003-07-31 | 2003-07-31 | 部分soi基板の製造方法 |
US10/675,950 US6956265B2 (en) | 2003-07-31 | 2003-10-02 | Semiconductor device and method for manufacturing partial SOI substrates |
US11/168,914 US7265017B2 (en) | 2003-07-31 | 2005-06-29 | Method for manufacturing partial SOI substrates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003283479A JP4167565B2 (ja) | 2003-07-31 | 2003-07-31 | 部分soi基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005051139A JP2005051139A (ja) | 2005-02-24 |
JP4167565B2 true JP4167565B2 (ja) | 2008-10-15 |
Family
ID=34101052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003283479A Expired - Fee Related JP4167565B2 (ja) | 2003-07-31 | 2003-07-31 | 部分soi基板の製造方法 |
Country Status (2)
Country | Link |
---|---|
US (2) | US6956265B2 (ja) |
JP (1) | JP4167565B2 (ja) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005268336A (ja) * | 2004-03-16 | 2005-09-29 | Nec Electronics Corp | 半導体装置及びその製造方法 |
JP3998677B2 (ja) * | 2004-10-19 | 2007-10-31 | 株式会社東芝 | 半導体ウェハの製造方法 |
US7327008B2 (en) * | 2005-01-24 | 2008-02-05 | International Business Machines Corporation | Structure and method for mixed-substrate SIMOX technology |
JP2006210432A (ja) * | 2005-01-25 | 2006-08-10 | Nec Electronics Corp | 基板の製造方法 |
US7384857B2 (en) * | 2005-02-25 | 2008-06-10 | Seiko Epson Corporation | Method to fabricate completely isolated silicon regions |
JP5090638B2 (ja) * | 2005-11-18 | 2012-12-05 | 株式会社Sumco | Soi基板を製造する方法 |
JP5038618B2 (ja) * | 2005-11-18 | 2012-10-03 | 株式会社Sumco | Soi基板の製造方法 |
JP2007142134A (ja) * | 2005-11-18 | 2007-06-07 | Sumco Corp | Soi基板の製造方法 |
US7804148B2 (en) * | 2006-02-16 | 2010-09-28 | International Business Machines Corporation | Opto-thermal mask including aligned thermal dissipative layer, reflective layer and transparent capping layer |
FR2897982B1 (fr) * | 2006-02-27 | 2008-07-11 | Tracit Technologies Sa | Procede de fabrication des structures de type partiellement soi, comportant des zones reliant une couche superficielle et un substrat |
US7666721B2 (en) * | 2006-03-15 | 2010-02-23 | International Business Machines Corporation | SOI substrates and SOI devices, and methods for forming the same |
US7285480B1 (en) * | 2006-04-07 | 2007-10-23 | International Business Machines Corporation | Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof |
KR102399469B1 (ko) | 2009-10-08 | 2022-05-19 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
KR102235725B1 (ko) | 2009-10-16 | 2021-04-05 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5662333A (en) | 1979-10-26 | 1981-05-28 | Toshiba Corp | Mos type semiconductor memory device and production thereof |
JPS61185950A (ja) | 1985-02-13 | 1986-08-19 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH03257948A (ja) | 1990-03-08 | 1991-11-18 | Matsushita Electron Corp | 半導体装置の製造方法 |
JPH05335408A (ja) | 1992-05-29 | 1993-12-17 | Sony Corp | 素子分離領域の形成方法 |
US5399507A (en) * | 1994-06-27 | 1995-03-21 | Motorola, Inc. | Fabrication of mixed thin-film and bulk semiconductor substrate for integrated circuit applications |
US5691230A (en) * | 1996-09-04 | 1997-11-25 | Micron Technology, Inc. | Technique for producing small islands of silicon on insulator |
JPH10125773A (ja) * | 1996-10-21 | 1998-05-15 | Nec Corp | 半導体装置の製造方法 |
US5956597A (en) | 1997-09-15 | 1999-09-21 | International Business Machines Corporation | Method for producing SOI & non-SOI circuits on a single wafer |
KR100282523B1 (ko) * | 1998-11-04 | 2001-02-15 | 김영환 | 정전방전 보호 특성을 개선한 에스오아이 반도체 소자 및 그 제조방법 |
JP3523531B2 (ja) * | 1999-06-18 | 2004-04-26 | シャープ株式会社 | 半導体装置の製造方法 |
US6406982B2 (en) * | 2000-06-05 | 2002-06-18 | Denso Corporation | Method of improving epitaxially-filled trench by smoothing trench prior to filling |
JP3984014B2 (ja) * | 2001-09-26 | 2007-09-26 | 株式会社東芝 | 半導体装置用基板を製造する方法および半導体装置用基板 |
JP4322453B2 (ja) * | 2001-09-27 | 2009-09-02 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP2003203967A (ja) * | 2001-12-28 | 2003-07-18 | Toshiba Corp | 部分soiウェーハの製造方法、半導体装置及びその製造方法 |
US6936851B2 (en) * | 2003-03-21 | 2005-08-30 | Tien Yang Wang | Semiconductor light-emitting device and method for manufacturing the same |
-
2003
- 2003-07-31 JP JP2003283479A patent/JP4167565B2/ja not_active Expired - Fee Related
- 2003-10-02 US US10/675,950 patent/US6956265B2/en not_active Expired - Fee Related
-
2005
- 2005-06-29 US US11/168,914 patent/US7265017B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20050023609A1 (en) | 2005-02-03 |
US6956265B2 (en) | 2005-10-18 |
US20050242397A1 (en) | 2005-11-03 |
US7265017B2 (en) | 2007-09-04 |
JP2005051139A (ja) | 2005-02-24 |
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