JP4145802B2 - 基板表面上に厚みの異なる酸化物層を形成する方法 - Google Patents

基板表面上に厚みの異なる酸化物層を形成する方法 Download PDF

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Publication number
JP4145802B2
JP4145802B2 JP2003572081A JP2003572081A JP4145802B2 JP 4145802 B2 JP4145802 B2 JP 4145802B2 JP 2003572081 A JP2003572081 A JP 2003572081A JP 2003572081 A JP2003572081 A JP 2003572081A JP 4145802 B2 JP4145802 B2 JP 4145802B2
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Prior art keywords
oxide
substrate
thickness
layer
predetermined
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Expired - Fee Related
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JP2003572081A
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English (en)
Japanese (ja)
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JP2005518675A5 (https=
JP2005518675A (ja
Inventor
ビークツォレク カルシュテン
グレーチュ フォーク
クリューゲル シュテファン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Priority claimed from DE10207122A external-priority patent/DE10207122B4/de
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/0134—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01342—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid by deposition, e.g. evaporation, ALD or laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01344—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid in a nitrogen-containing ambient, e.g. N2O oxidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2003572081A 2002-02-20 2002-12-20 基板表面上に厚みの異なる酸化物層を形成する方法 Expired - Fee Related JP4145802B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10207122A DE10207122B4 (de) 2002-02-20 2002-02-20 Ein Verfahren zur Herstellung von Schichten aus Oxid auf einer Oberfläche eines Substrats
US10/208,308 US6703278B2 (en) 2002-02-20 2002-07-30 Method of forming layers of oxide on a surface of a substrate
PCT/US2002/040807 WO2003073491A1 (en) 2002-02-20 2002-12-20 Method of forming layers of oxide of different thicknesses on a surface of a substrate

Publications (3)

Publication Number Publication Date
JP2005518675A JP2005518675A (ja) 2005-06-23
JP2005518675A5 JP2005518675A5 (https=) 2006-09-07
JP4145802B2 true JP4145802B2 (ja) 2008-09-03

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JP2003572081A Expired - Fee Related JP4145802B2 (ja) 2002-02-20 2002-12-20 基板表面上に厚みの異なる酸化物層を形成する方法

Country Status (6)

Country Link
EP (1) EP1476899B1 (https=)
JP (1) JP4145802B2 (https=)
CN (1) CN1315162C (https=)
AU (1) AU2002351408A1 (https=)
TW (1) TWI278038B (https=)
WO (1) WO2003073491A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100678321B1 (ko) 2005-12-14 2007-02-02 동부일렉트로닉스 주식회사 서로 다른 두께의 게이트 유전층들을 형성하는 방법
DE102017104906A1 (de) * 2017-03-08 2018-09-13 Olav Birlem Anordnung und Verfahren zum Bereitstellen einer Vielzahl von Nanodrähten
CN108257860A (zh) * 2018-01-19 2018-07-06 武汉新芯集成电路制造有限公司 一种栅极氧化层的制作方法
US11430701B2 (en) * 2020-09-25 2022-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Gate oxide structures in semiconductor devices
CN114765107A (zh) * 2021-01-14 2022-07-19 长鑫存储技术有限公司 半导体结构的制备方法及半导体结构
US12119222B2 (en) 2021-01-14 2024-10-15 Changxin Memory Technologies, Inc. Method for preparing semiconductor structure and semiconductor structure

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
US6087236A (en) * 1998-11-24 2000-07-11 Intel Corporation Integrated circuit with multiple gate dielectric structures
US6235590B1 (en) * 1998-12-18 2001-05-22 Lsi Logic Corporation Fabrication of differential gate oxide thicknesses on a single integrated circuit chip
KR20010004417A (ko) * 1999-06-28 2001-01-15 김영환 반도체장치의 듀얼 게이트산화막 형성 방법

Also Published As

Publication number Publication date
EP1476899A1 (en) 2004-11-17
CN1315162C (zh) 2007-05-09
TW200304187A (en) 2003-09-16
EP1476899B1 (en) 2007-03-07
TWI278038B (en) 2007-04-01
CN1620718A (zh) 2005-05-25
AU2002351408A1 (en) 2003-09-09
JP2005518675A (ja) 2005-06-23
WO2003073491A1 (en) 2003-09-04

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