JP3967321B2 - 半導体集積回路 - Google Patents
半導体集積回路 Download PDFInfo
- Publication number
- JP3967321B2 JP3967321B2 JP2003550364A JP2003550364A JP3967321B2 JP 3967321 B2 JP3967321 B2 JP 3967321B2 JP 2003550364 A JP2003550364 A JP 2003550364A JP 2003550364 A JP2003550364 A JP 2003550364A JP 3967321 B2 JP3967321 B2 JP 3967321B2
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- JP
- Japan
- Prior art keywords
- transistor
- potential
- transistors
- resistor
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/028—Arrangements specific to the transmitter end
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Amplifiers (AREA)
Description
図4に、本発明の一実施形態に係る半導体集積回路に含まれるラインドライバの構成を示す。図4に示すように、このラインドライバは、ドライバ回路42と、ドライバ回路42の動作を制御するためのレプリカ回路41とによって構成される。
42 ドライバ回路
401〜408 ノード
R T 終端抵抗
QN41〜QN50 NチャネルMOSトランジスタ
OP41 オペアンプ
Claims (6)
- 直列に接続された第1のトランジスタ及び第2のトランジスタと、直列に接続された第3のトランジスタ及び第4のトランジスタとを含み、差動入力信号が供給されてスイッチング動作を行うことにより、前記第1及び第2のトランジスタの接続点と前記第3及び第4のトランジスタの接続点との間に接続される負荷に差動出力信号を供給する出力回路と、第1の電源電位と前記第1及び第3のトランジスタとの間に接続された第5のトランジスタと、前記第2及び第4のトランジスタと第2の電源電位との間に接続され、ゲートに印加される第1のリファレンス電位に従って前記出力回路に流れる電流を決定する第6のトランジスタとを備えるドライバ回路と、
第1の電源電位に接続された第7のトランジスタと、第2の電源電位に接続されて前記第6のトランジスタと共にカレントミラー回路を構成し、前記第1のリファレンス電位がゲートに印加されて、前記第6のトランジスタに流れる電流に比例する電流を流す第8のトランジスタと、前記第7のトランジスタと前記第8のトランジスタとの間に直列に接続された第9のトランジスタ及び互いに等しい抵抗値を有する第1の抵抗及び第2の抵抗及び第10のトランジスタと、前記第1の抵抗と前記第2の抵抗との接続点における電位と第2のリファレンス電位との差を増幅して、増幅された電位を前記第5及び第7のトランジスタのゲートにフィードバックすることにより、前記負荷に供給される2つの出力信号の電位の平均値が出力信号の振幅によらずに一定となるように制御する差動増幅器とを備えるドライバ回路用制御回路と、
を具備する半導体集積回路。 - 前記第1の電源電位が前記第2の電源電位よりも高く、前記第1〜第10のトランジスタの各々がNチャネルMOSトランジスタを含む、請求項1記載の半導体集積回路。
- nを0より大きい数とするときに、前記第7〜10のトランジスタに流れる電流が、前記第5及び第6のトランジスタに流れる電流の1/nである、請求項1記載の半導体集積回路。
- 前記第7、第8、第9、第10のトランジスタが、前記第5、第6、第1又は第3、第2又は第4のトランジスタのサイズの1/nのサイズをそれぞれ有する、請求項3記載の半導体集積回路。
- 前記第1及び第2の抵抗の各々が、前記出力回路に接続される終端抵抗の抵抗値の(n/2)倍の抵抗値を有する、請求項3記載の半導体集積回路。
- 前記差動増幅器が、
前記第2のリファレンス電位が供給される非反転入力端子と、
前記第1の抵抗と前記第2の抵抗との接続点における電位が供給される反転入力端子と、
前記第5及び第7のトランジスタのゲートに出力電位を供給する出力端子と、
を有する、請求項1記載の半導体集積回路。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2001/010725 WO2003049291A1 (fr) | 2001-12-07 | 2001-12-07 | Circuit integre a semi-conducteur |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2003049291A1 JPWO2003049291A1 (ja) | 2005-04-21 |
JP3967321B2 true JP3967321B2 (ja) | 2007-08-29 |
Family
ID=11738008
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003550364A Expired - Fee Related JP3967321B2 (ja) | 2001-12-07 | 2001-12-07 | 半導体集積回路 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7129756B2 (ja) |
EP (1) | EP1465343A1 (ja) |
JP (1) | JP3967321B2 (ja) |
KR (1) | KR100740496B1 (ja) |
CN (1) | CN1252927C (ja) |
WO (1) | WO2003049291A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009152944A (ja) * | 2007-12-21 | 2009-07-09 | Kawasaki Microelectronics Inc | 出力ドライバ回路 |
JP2009165085A (ja) * | 2008-01-10 | 2009-07-23 | Kawasaki Microelectronics Inc | 出力ドライバ回路 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3808026B2 (ja) * | 2002-10-23 | 2006-08-09 | 株式会社ルネサステクノロジ | 半導体装置 |
JP3792207B2 (ja) * | 2003-03-25 | 2006-07-05 | 沖電気工業株式会社 | 電流駆動型差動ドライバ及び電流駆動型差動ドライバを用いたデータ送信方法 |
JP3948446B2 (ja) | 2003-09-03 | 2007-07-25 | セイコーエプソン株式会社 | 半導体装置 |
JP2005303830A (ja) * | 2004-04-14 | 2005-10-27 | Renesas Technology Corp | 差動出力回路 |
US7342420B2 (en) * | 2004-09-24 | 2008-03-11 | Integrated Device Technology, Inc. | Low power output driver |
JP4509737B2 (ja) * | 2004-10-28 | 2010-07-21 | 株式会社東芝 | 差動信号生成回路および差動信号送信回路 |
US20080246511A1 (en) * | 2005-04-28 | 2008-10-09 | Satoshi Miura | Differential Drive Circuit and Electronic Apparatus Incorporating the Same |
DE102005022338A1 (de) * | 2005-05-13 | 2006-11-16 | Texas Instruments Deutschland Gmbh | Integrierte Treiberschaltungsstruktur |
US7330056B1 (en) * | 2005-12-06 | 2008-02-12 | Exar Corporation | Low power CMOS LVDS driver |
JP4858959B2 (ja) | 2006-06-06 | 2012-01-18 | ルネサスエレクトロニクス株式会社 | 差動信号駆動回路及び差動信号駆動方法 |
US20080218292A1 (en) * | 2007-03-08 | 2008-09-11 | Dong-Uk Park | Low voltage data transmitting circuit and associated methods |
JP2009049671A (ja) * | 2007-08-20 | 2009-03-05 | Rohm Co Ltd | 出力制限回路、d級パワーアンプ、音響機器 |
US8058924B1 (en) * | 2009-01-29 | 2011-11-15 | Xilinx, Inc. | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device |
US8222954B1 (en) * | 2009-01-29 | 2012-07-17 | Xilinx, Inc. | Method and apparatus for a process, voltage, and temperature variation tolerant semiconductor device |
KR101139633B1 (ko) * | 2010-08-04 | 2012-05-15 | 성균관대학교산학협력단 | 임피던스 매칭 및 프리앰퍼시스를 위한 전압 조절기, 임피던스 매칭 및 프리앰퍼시스를 위한 전압 조절 방법, 이 전압 조절기를 포함하는 전압모드 드라이버 및 이 전압 조절 방법을 이용하는 전압모드 드라이버 |
CN101997539B (zh) * | 2010-11-22 | 2012-08-22 | 北京时代民芯科技有限公司 | 一种可编程逻辑电路 |
US8760189B2 (en) * | 2011-09-29 | 2014-06-24 | Qualcomm Incorporated | Apparatus to implement symmetric single-ended termination in differential voltage-mode drivers |
KR101332072B1 (ko) * | 2011-11-17 | 2014-01-22 | 서울시립대학교 산학협력단 | 전원장치에 사용되는 ic 회로 |
US8928365B2 (en) * | 2012-10-23 | 2015-01-06 | Qualcomm Incorporated | Methods and devices for matching transmission line characteristics using stacked metal oxide semiconductor (MOS) transistors |
CN104253609B (zh) * | 2013-06-28 | 2017-11-28 | 比亚迪股份有限公司 | 一种低电压差分信号驱动电路 |
WO2016035192A1 (ja) * | 2014-09-04 | 2016-03-10 | 株式会社ソシオネクスト | 送信回路及び半導体集積回路 |
JP2021153281A (ja) * | 2020-03-25 | 2021-09-30 | キオクシア株式会社 | 半導体集積回路及び受信装置 |
US11075636B1 (en) * | 2020-03-26 | 2021-07-27 | Nxp Usa, Inc. | Differential output driver circuit and method of operation |
CN115454190A (zh) * | 2022-09-30 | 2022-12-09 | 湖北三江航天万峰科技发展有限公司 | 一种lvds驱动电路 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6118438A (en) * | 1997-03-18 | 2000-09-12 | Ati Technologies, Inc. | Low comment mode impedence differential driver and applications thereof |
JP3334548B2 (ja) | 1997-03-21 | 2002-10-15 | ヤマハ株式会社 | 定電流駆動回路 |
US6111431A (en) * | 1998-05-14 | 2000-08-29 | National Semiconductor Corporation | LVDS driver for backplane applications |
JP3171175B2 (ja) | 1998-12-08 | 2001-05-28 | 日本電気株式会社 | 差動トライステート発生方法及び差動トライステート回路 |
US6600346B1 (en) * | 2002-07-30 | 2003-07-29 | National Semiconductor Corporation | Low voltage differential swing (LVDS) signal driver circuit with low PVT and load sensitivity |
-
2001
- 2001-12-07 WO PCT/JP2001/010725 patent/WO2003049291A1/ja not_active Application Discontinuation
- 2001-12-07 EP EP01274914A patent/EP1465343A1/en not_active Withdrawn
- 2001-12-07 KR KR1020047008631A patent/KR100740496B1/ko active IP Right Grant
- 2001-12-07 CN CNB018238599A patent/CN1252927C/zh not_active Expired - Lifetime
- 2001-12-07 US US10/497,457 patent/US7129756B2/en not_active Expired - Lifetime
- 2001-12-07 JP JP2003550364A patent/JP3967321B2/ja not_active Expired - Fee Related
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009152944A (ja) * | 2007-12-21 | 2009-07-09 | Kawasaki Microelectronics Inc | 出力ドライバ回路 |
JP2009165085A (ja) * | 2008-01-10 | 2009-07-23 | Kawasaki Microelectronics Inc | 出力ドライバ回路 |
Also Published As
Publication number | Publication date |
---|---|
CN1252927C (zh) | 2006-04-19 |
EP1465343A1 (en) | 2004-10-06 |
WO2003049291A1 (fr) | 2003-06-12 |
JPWO2003049291A1 (ja) | 2005-04-21 |
KR20040071175A (ko) | 2004-08-11 |
KR100740496B1 (ko) | 2007-07-19 |
US7129756B2 (en) | 2006-10-31 |
CN1561577A (zh) | 2005-01-05 |
US20050007150A1 (en) | 2005-01-13 |
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