JP3920415B2 - 不揮発性半導体メモリ装置 - Google Patents

不揮発性半導体メモリ装置 Download PDF

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Publication number
JP3920415B2
JP3920415B2 JP19756997A JP19756997A JP3920415B2 JP 3920415 B2 JP3920415 B2 JP 3920415B2 JP 19756997 A JP19756997 A JP 19756997A JP 19756997 A JP19756997 A JP 19756997A JP 3920415 B2 JP3920415 B2 JP 3920415B2
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JP
Japan
Prior art keywords
memory cell
transistors
cell transistor
write
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP19756997A
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English (en)
Japanese (ja)
Other versions
JPH10334676A (ja
JPH10334676A5 (enExample
Inventor
雅典 梶谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP19756997A priority Critical patent/JP3920415B2/ja
Priority to US09/049,311 priority patent/US6285589B1/en
Publication of JPH10334676A publication Critical patent/JPH10334676A/ja
Publication of JPH10334676A5 publication Critical patent/JPH10334676A5/ja
Application granted granted Critical
Publication of JP3920415B2 publication Critical patent/JP3920415B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5634—Reference cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
JP19756997A 1997-03-31 1997-07-23 不揮発性半導体メモリ装置 Expired - Fee Related JP3920415B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP19756997A JP3920415B2 (ja) 1997-03-31 1997-07-23 不揮発性半導体メモリ装置
US09/049,311 US6285589B1 (en) 1997-03-31 1998-03-27 Non-volatile semiconductor memory apparatus

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP8147997 1997-03-31
JP9-81479 1997-03-31
JP19756997A JP3920415B2 (ja) 1997-03-31 1997-07-23 不揮発性半導体メモリ装置

Publications (3)

Publication Number Publication Date
JPH10334676A JPH10334676A (ja) 1998-12-18
JPH10334676A5 JPH10334676A5 (enExample) 2005-09-08
JP3920415B2 true JP3920415B2 (ja) 2007-05-30

Family

ID=26422502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19756997A Expired - Fee Related JP3920415B2 (ja) 1997-03-31 1997-07-23 不揮発性半導体メモリ装置

Country Status (2)

Country Link
US (1) US6285589B1 (enExample)
JP (1) JP3920415B2 (enExample)

Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6928001B2 (en) 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
IL148959A (en) * 2001-04-05 2006-09-05 Saifun Semiconductors Ltd Architecture and scheme for a non-strobed read sequence
US6535434B2 (en) 2001-04-05 2003-03-18 Saifun Semiconductors Ltd. Architecture and scheme for a non-strobed read sequence
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
TW559814B (en) * 2001-05-31 2003-11-01 Semiconductor Energy Lab Nonvolatile memory and method of driving the same
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US7190620B2 (en) * 2002-01-31 2007-03-13 Saifun Semiconductors Ltd. Method for operating a memory device
KR100878527B1 (ko) * 2002-07-08 2009-01-13 삼성전자주식회사 Ｎａｎｄ 형 플래쉬 메모리 제어기와 제어기에서 사용되는클럭제어방법
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6963505B2 (en) * 2002-10-29 2005-11-08 Aifun Semiconductors Ltd. Method circuit and system for determining a reference voltage
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6992932B2 (en) 2002-10-29 2006-01-31 Saifun Semiconductors Ltd Method circuit and system for read error detection in a non-volatile memory array
US6967896B2 (en) 2003-01-30 2005-11-22 Saifun Semiconductors Ltd Address scramble
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US6909638B2 (en) * 2003-04-30 2005-06-21 Freescale Semiconductor, Inc. Non-volatile memory having a bias on the source electrode for HCI programming
JP4278438B2 (ja) * 2003-05-27 2009-06-17 三洋電機株式会社 不揮発性半導体記憶装置及びその制御方法
US20050027567A1 (en) * 2003-07-29 2005-02-03 Taha Amer Jamil System and method for health care data collection and management
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7652930B2 (en) 2004-04-01 2010-01-26 Saifun Semiconductors Ltd. Method, circuit and system for erasing one or more non-volatile memory cells
US7755938B2 (en) * 2004-04-19 2010-07-13 Saifun Semiconductors Ltd. Method for reading a memory array with neighbor effect cancellation
US7366025B2 (en) * 2004-06-10 2008-04-29 Saifun Semiconductors Ltd. Reduced power programming of non-volatile cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7257025B2 (en) * 2004-12-09 2007-08-14 Saifun Semiconductors Ltd Method for reading non-volatile memory cells
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (en) 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US8400841B2 (en) 2005-06-15 2013-03-19 Spansion Israel Ltd. Device to program adjacent storage cells of different NROM cells
JP2007027760A (ja) 2005-07-18 2007-02-01 Saifun Semiconductors Ltd 高密度不揮発性メモリアレイ及び製造方法
US7180795B1 (en) * 2005-08-05 2007-02-20 Atmel Corporation Method of sensing an EEPROM reference cell
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
JP4998934B2 (ja) * 2006-03-30 2012-08-15 ルネサスエレクトロニクス株式会社 半導体記憶装置の製造方法
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7590001B2 (en) 2007-12-18 2009-09-15 Saifun Semiconductors Ltd. Flash memory with optimized write sector spares
KR102140592B1 (ko) * 2013-10-18 2020-08-03 에스케이하이닉스 주식회사 데이터 저장 장치
CN109643572A (zh) * 2016-09-12 2019-04-16 株式会社半导体能源研究所 存储装置及其工作方法、半导体装置、电子构件以及电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608679A (en) * 1994-06-02 1997-03-04 Intel Corporation Fast internal reference cell trimming for flash EEPROM memory
US5712815A (en) * 1996-04-22 1998-01-27 Advanced Micro Devices, Inc. Multiple bits per-cell flash EEPROM capable of concurrently programming and verifying memory cells and reference cells
US5790453A (en) * 1996-10-24 1998-08-04 Micron Quantum Devices, Inc. Apparatus and method for reading state of multistate non-volatile memory cells

Also Published As

Publication number Publication date
JPH10334676A (ja) 1998-12-18
US6285589B1 (en) 2001-09-04

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