JP3899059B2 - 低抵抗高密度信号線をする電子パッケージおよびその製造方法 - Google Patents
低抵抗高密度信号線をする電子パッケージおよびその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims description 114
- 238000000034 method Methods 0.000 claims description 13
- 238000004100 electronic packaging Methods 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 description 19
- 239000004020 conductor Substances 0.000 description 15
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- H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
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- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
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- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
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- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Description
12 基板
14、301、401 集積回路(ダイ)
15 半田ボール
16 電気部品接続
50 基板の上面
20、22、24 垂直信号線(ビア)
52、54、56、58、60、62、64、66、68 水平な層
200、202、204、206、208、210、101 基準面
112、116、118 高密度高抵抗水平信号線(薄い信号線)
114、105、102 低密度低抵抗水平信号線(厚い信号線)
120、122、124、130、148、150 垂直信号線
126、128、140 接続セグメント
211、212、214 基準面
151、160 信号線
154 ダイ・シャドウ領域(高密度高抵抗信号配線)
156 低密度低抵抗配線領域
168 信号線接続
164 基板材料
162 基板領域
Claims (9)
- 電子パッケージ・デバイスであって、
複数の接続要素を表面に含む電気部品と、
前記電気部品の下に位置する上面および底面を有し、かつ前記電気部品の前記接続要素を前記上面で受けるように構成され、複数の水平層を含む基板と、
前記複数の水平層に含まれる複数の導電性水平信号線であって、第1の水平信号線及び第2の水平信号線を含み、前記第1の水平信号線が第1の水平層に含まれ、第1の垂直方向厚さと第1の抵抗値を有し、前記第2の水平信号線が第2の水平層に含まれ、前記第1の水平信号線の前記第1の垂直方向厚さよりも大きな第2の垂直方向厚さおよび前記第1の水平信号線の前記第1の抵抗値よりも小さな第2の抵抗値を有し、前記第2の水平層は前記第1の水平層の下に位置する、複数の導電性水平信号線と、
前記基板内の前記複数の水平層に沿って形成される複数の基準面であって、垂直方向厚さを有し、少なくとも1つの前記基準面の導電性金属に電源が接続される、複数の基準面と、
特定の直径を有する複数の垂直な導電性ビアであって、前記第1の水平層及び前記第2の水平層を貫通して前記接続要素に接続しかつ前記導電性水平信号線の少なくとも1つに接続する第1の垂直ビアを含む、複数の垂直な導電性ビアと、
前記基板の下に位置し、接続部材を有する絶縁基板であって、前記垂直な導電性ビアが前記絶縁基板の前記接続部材に接続されて終わる、絶縁基板と、
を備え
前記第1の水平信号線は前記第2の水平層に含まれる基準面の上方に配置され、前記第2の水平信号線は前記第1の水平層に含まれる基準面の下方に配置され、前記基板内の前記複数の基準面は前記導電性水平信号線が占めない領域で分割され、前記分割により前記基板が前記第1の水平信号線からなる第1の基板領域と前記第2の水平信号線からなる第2の基板領域に分けられる、
電子パッケージ・デバイス。 - 前記複数の基準面が互いに異なる電圧を有する前記基準面を含む、請求項1に記載のデバイス。
- 前記複数の基準面がそれぞれ電圧値を有し、実質的に同様な電圧値を有する前記基準面が接続されている、請求項1に記載のデバイス。
- 前記水平信号線において、前記第1の水平信号線が前記複数の水平層のうち異なる水平層に含まれる第1の基準面と第2の基準面の間に位置するように、前記複数の基準面の少なくとも2つの間に位置し、前記第1の基準面が前記第1の水平層に沿って位置しかつ第1の垂直方向厚さを含み、前記第2の基準面が前記第2の水平層に沿って位置しかつ第2の垂直方向厚さを含む、請求項1に記載のデバイス。
- 前記基板は、前記基準面が前記基板の前記底面に近くなるほど前記基準面の前記垂直方向厚さが増すような複数の基準面を含む、請求項1に記載のデバイス。
- 前記第1の水平信号線が前記第1の垂直方向厚さを含み、前記第2の水平信号線が前記第2の垂直方向厚さを含み、前記基板中で前記第2の水平層の下に位置する第3の水平層に沿って走る第3の水平信号線が前記第1の垂直方向厚さに実質的に等しい第3の垂直方向厚さを含み、そして、第4の水平信号線が前記基板中で前記第3の水平層の下に位置する第4の水平層に沿って走りかつ前記第2の垂直方向厚さに実質的に等しい第4の垂直方向厚さを含むように、前記複数の前記導電性水平信号線が厚さを交互にする、請求項1に記載のデバイス。
- 前記複数の垂直な導電性ビアは、前記第1の水平信号線と前記第2の水平信号線を接続する第2の垂直ビアをさらに含む、請求項1に記載のデバイス。
- 電子パッケージ・デバイスであって、
複数の接続要素を表面に含む集積回路と、
前記集積回路の下に位置する上面および底面を有し、かつ前記集積回路の前記接続要素を前記上面で受けるように構成され、 複数の水平層を含む基板と、、
前記複数の水平層に含まれる複数の導電性水平信号線であって、第1の水平信号線及び第2の水平信号線を含み、前記第1の水平信号線が第1の水平層に含まれ、第1の垂直方向厚さを有し、前記第2の水平信号線が第2の水平層に含まれ、前記第1の水平信号線の前記第1の垂直方向厚さよりも大きな第2の垂直方向厚さを有し、前記第2の水平層は前記第1の水平層の下に位置し、前記第1の水平信号線は前記第2の水平信号に比べて高密度高抵抗である、複数の導電性水平信号線と、
前記基板内の前記複数の水平層に沿って形成される複数の基準面であって、垂直方向厚さを有し、少なくとも1つの前記基準面の導電性金属に電源が接続され、前記第1の水平信号線が前記複数の水平層のうち異なる水平層に含まれる第1の基準面と第2の基準面の間に位置するように、前記複数の基準面の少なくとも2つの間に位置し、前記第1の基準面が前記第1の水平層に沿って位置しかつ第1の垂直方向厚さを含み、前記第2の基準面が前記第2の水平層に沿って位置しかつ第2の垂直方向厚さを含む、複数の基準面と、
特定の直径を有する複数の垂直な導電性ビアであって、前記集積回路の前記接続要素に接続しかつ前記導電性水平信号線の少なくとも1つに接続する複数の第1の垂直ビアと、前記第1の水平信号線と前記第2の水平信号線を接続する複数の第2の垂直ビアとを含む、複数の垂直な導電性ビアと、
前記基板の下に位置し、接続部材を有する回路基板であって、前記垂直な導電性ビアが前記回路基板の前記接続部材に接続されて終わる、回路基板と、
を備え
前記第1の水平信号線は前記第2の水平層に含まれる基準面の上方に配置され、前記第2の水平信号線は前記第1の水平層に含まれる基準面の下方に配置され、前記基板内の前記複数の基準面は前記導電性水平信号線が占めない領域で分割され、前記分割により前記基板が前記第1の水平信号線からなる第1の基板領域と前記第2の水平信号線からなる第2の基板領域に分けられる、
電子パッケージ・デバイス。 - 電子パッケージングの方法であって、
複数の接続要素を表面に設けた集積回路の下に位置し、かつ前記集積回路の前記接続要素に結合される基板において、複数の水平層を形成するステップであって、前記水平層は第1の水平層と第2の水平層を含む、ステップと、
前記基板内の前記水平層に複数の導電性水平信号線を形成するステップであって、前記水平信号線は前記第1の水平層に形成される第1の水平信号線及び前記第2の水平層に形成される第2の水平信号線を有し、前記第1の水平信号線が垂直方向厚さを有しかつ前記第2の水平信号線が前記第1の水平信号線の前記垂直方向厚さよりも大きな垂直方向厚さを有する、ステップと、
前記複数の水平層に沿って垂直方向厚さを有する複数の基準面を前記基板内に形成するステップと、
前記複数の基準面のうちの少なくとも1つに電源を接続するために導電性金属を形成するステップと、
特定の直径を有する複数の垂直な導電性ビアを形成するステップであって、前記複数の垂直な導電性ビアは、第1の導電性ビア及び第2の導電性ビアを含み、前記第1の導電性ビアは前記集積回路の前記接続要素に接続しかつ前記第1の水平層と前記第2の水平層を貫通して前記水平信号線の少なくとも1つと接続し、前記第2の導電性ビアは前記第1の水平信号線と前記第2の水平信号線とに接続する、ステップと、
前記基板の下に位置する回路基板の接続部材と前記第2の水平信号線とを前記垂直な導電性ビアで接続するステップと、を含み、
前記第1の水平信号線は前記第2の水平層に含まれる基準面の上方に配置され、前記第2の水平信号線は前記第1の水平層に含まれる基準面の下方に配置され、前記第1の水平信号線が第1の基準面と第2の基準面の間に位置するように、前記複数の基準面の少なくとも2つの間に位置し、前記第1の基準面が前記第1の水平層に沿って位置しかつ第1の垂直方向厚さを含み、前記第2の基準面が前記第2の水平層に沿って位置しかつ第2の垂直方向厚さを含み、前記基板内の前記複数の基準面は前記導電性水平信号線が占めない領域で分割され、前記分割により前記第1の水平信号線からなる第1の基板領域と前記第2の水平信号線からなる第2の基板領域に分けられる、方法。
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US10/246,147 US6762367B2 (en) | 2002-09-17 | 2002-09-17 | Electronic package having high density signal wires with low resistance |
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JP3899059B2 true JP3899059B2 (ja) | 2007-03-28 |
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US20080093726A1 (en) * | 2006-10-23 | 2008-04-24 | Francesco Preda | Continuously Referencing Signals over Multiple Layers in Laminate Packages |
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JP2013093345A (ja) * | 2011-10-24 | 2013-05-16 | Hitachi Ltd | 光モジュールおよび多層基板 |
DE102012214982B4 (de) * | 2012-08-23 | 2021-06-02 | Vitesco Technologies GmbH | Leiterplatine |
KR20140121181A (ko) * | 2013-04-05 | 2014-10-15 | 삼성전자주식회사 | 인쇄회로기판 및 이를 포함하는 메모리 모듈 |
JPWO2015076121A1 (ja) * | 2013-11-20 | 2017-03-16 | 株式会社村田製作所 | 多層配線基板およびこれを備えるプローブカード |
US9832863B2 (en) * | 2015-09-25 | 2017-11-28 | Intel Corporation | Method of fabricating a stretchable computing device |
DE102015224073A1 (de) * | 2015-12-02 | 2017-06-08 | Zf Friedrichshafen Ag | Mehrfunktionale Hochstromleiterplatte |
KR102542594B1 (ko) | 2016-12-16 | 2023-06-14 | 삼성전자 주식회사 | 다층 인쇄 회로 기판 및 이를 포함하는 전자 장치 |
JP6981022B2 (ja) * | 2017-03-17 | 2021-12-15 | セイコーエプソン株式会社 | プリント回路板および電子機器 |
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JP2004111967A (ja) | 2004-04-08 |
US6762367B2 (en) | 2004-07-13 |
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