JP3869849B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP3869849B2
JP3869849B2 JP2006072498A JP2006072498A JP3869849B2 JP 3869849 B2 JP3869849 B2 JP 3869849B2 JP 2006072498 A JP2006072498 A JP 2006072498A JP 2006072498 A JP2006072498 A JP 2006072498A JP 3869849 B2 JP3869849 B2 JP 3869849B2
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JP
Japan
Prior art keywords
metal layer
semiconductor device
metal
semiconductor element
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2006072498A
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English (en)
Japanese (ja)
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JP2006196922A (ja
JP2006196922A5 (https=
Inventor
浩 木村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Torex Semiconductor Ltd
Maxell Ltd
Original Assignee
Kyushu Hitachi Maxell Ltd
Torex Semiconductor Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Hitachi Maxell Ltd, Torex Semiconductor Ltd filed Critical Kyushu Hitachi Maxell Ltd
Priority to JP2006072498A priority Critical patent/JP3869849B2/ja
Publication of JP2006196922A publication Critical patent/JP2006196922A/ja
Publication of JP2006196922A5 publication Critical patent/JP2006196922A5/ja
Application granted granted Critical
Publication of JP3869849B2 publication Critical patent/JP3869849B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2006072498A 2000-04-25 2006-03-16 半導体装置の製造方法 Expired - Lifetime JP3869849B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006072498A JP3869849B2 (ja) 2000-04-25 2006-03-16 半導体装置の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000124102 2000-04-25
JP2006072498A JP3869849B2 (ja) 2000-04-25 2006-03-16 半導体装置の製造方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2001078791A Division JP2002016181A (ja) 2000-04-25 2001-03-19 半導体装置、その製造方法、及び電着フレーム

Publications (3)

Publication Number Publication Date
JP2006196922A JP2006196922A (ja) 2006-07-27
JP2006196922A5 JP2006196922A5 (https=) 2006-09-21
JP3869849B2 true JP3869849B2 (ja) 2007-01-17

Family

ID=36802682

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006072498A Expired - Lifetime JP3869849B2 (ja) 2000-04-25 2006-03-16 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP3869849B2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5098452B2 (ja) * 2007-06-11 2012-12-12 住友金属鉱山株式会社 半導体装置の製造方法
JP5151438B2 (ja) * 2007-12-10 2013-02-27 大日本印刷株式会社 半導体装置およびその製造方法、ならびに半導体装置用基板およびその製造方法
US8866296B2 (en) 2009-06-24 2014-10-21 Aoi Electronics Co., Ltd. Semiconductor device comprising thin-film terminal with deformed portion
EP2337068A1 (en) 2009-12-18 2011-06-22 Nxp B.V. Pre-soldered leadless package
JP5779748B2 (ja) 2010-11-02 2015-09-16 リコー電子デバイス株式会社 半導体パッケージ及び電子部品実装体
TWI533380B (zh) * 2011-05-03 2016-05-11 旭德科技股份有限公司 封裝結構及其製作方法
JP2012084938A (ja) * 2012-02-03 2012-04-26 Sumitomo Metal Mining Co Ltd 半導体装置製造用基板

Also Published As

Publication number Publication date
JP2006196922A (ja) 2006-07-27

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