JP3847940B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3847940B2 JP3847940B2 JP04205698A JP4205698A JP3847940B2 JP 3847940 B2 JP3847940 B2 JP 3847940B2 JP 04205698 A JP04205698 A JP 04205698A JP 4205698 A JP4205698 A JP 4205698A JP 3847940 B2 JP3847940 B2 JP 3847940B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- region
- insulating film
- forming
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04205698A JP3847940B2 (ja) | 1998-02-24 | 1998-02-24 | 半導体装置の製造方法 |
| US09/105,958 US6184083B1 (en) | 1997-06-30 | 1998-06-29 | Semiconductor device and method of manufacturing the same |
| US09/688,989 US7361960B1 (en) | 1997-06-30 | 2000-10-17 | Semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP04205698A JP3847940B2 (ja) | 1998-02-24 | 1998-02-24 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH11243150A JPH11243150A (ja) | 1999-09-07 |
| JPH11243150A5 JPH11243150A5 (enrdf_load_html_response) | 2004-12-09 |
| JP3847940B2 true JP3847940B2 (ja) | 2006-11-22 |
Family
ID=12625460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP04205698A Expired - Fee Related JP3847940B2 (ja) | 1997-06-30 | 1998-02-24 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3847940B2 (enrdf_load_html_response) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4237332B2 (ja) | 1999-04-30 | 2009-03-11 | 株式会社東芝 | 半導体装置の製造方法 |
| KR100511908B1 (ko) * | 1999-12-22 | 2005-09-02 | 주식회사 하이닉스반도체 | 다마신 및 자기 정렬 콘택 공정을 이용한 반도체 소자의제조방법 |
| WO2001071807A1 (en) | 2000-03-24 | 2001-09-27 | Fujitsu Limited | Semiconductor device and method of manufacture thereof |
| KR100431085B1 (ko) * | 2001-06-29 | 2004-05-12 | 주식회사 하이닉스반도체 | 반도체 소자의 트랜지스터 제조 방법 |
| US6624043B2 (en) * | 2001-09-24 | 2003-09-23 | Sharp Laboratories Of America, Inc. | Metal gate CMOS and method of manufacturing the same |
| KR100607728B1 (ko) * | 2002-09-07 | 2006-08-01 | 동부일렉트로닉스 주식회사 | 반도체 소자의 다마신 게이트 프로세스 형성방법 |
| US7056794B2 (en) * | 2004-01-09 | 2006-06-06 | International Business Machines Corporation | FET gate structure with metal gate electrode and silicide contact |
| US7060568B2 (en) * | 2004-06-30 | 2006-06-13 | Intel Corporation | Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit |
| US7148548B2 (en) * | 2004-07-20 | 2006-12-12 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
| US7977751B2 (en) | 2007-02-06 | 2011-07-12 | Sony Corporation | Insulated gate field effect transistor and a method of manufacturing the same |
| JP4367523B2 (ja) * | 2007-02-06 | 2009-11-18 | ソニー株式会社 | 絶縁ゲート電界効果トランジスタ及びその製造方法 |
-
1998
- 1998-02-24 JP JP04205698A patent/JP3847940B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH11243150A (ja) | 1999-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2875093B2 (ja) | 半導体装置 | |
| KR101205173B1 (ko) | 반도체 소자의 형성 방법 | |
| JP2003536259A (ja) | ダマシーンアーキテクチャーにおいて自己位置合わせされたソース・ドレイン・ゲートを有してなる電子素子の形成方法 | |
| JP3847940B2 (ja) | 半導体装置の製造方法 | |
| JP3420145B2 (ja) | 半導体集積回路装置の製造方法 | |
| US6599795B2 (en) | Method of manufacturing semiconductor device including a step of forming a silicide layer, and semiconductor device manufactured thereby | |
| JP3215320B2 (ja) | 半導体装置の製造方法 | |
| US6503789B1 (en) | Contact structure for a semiconductor device and manufacturing method thereof | |
| US8013361B2 (en) | Semiconductor device and method for fabricating the same | |
| JPH11135779A (ja) | 半導体装置及びその製造方法 | |
| US5939758A (en) | Semiconductor device with gate electrodes having conductive films | |
| JP2003060069A (ja) | 二重ゲート酸化膜を有する半導体素子の製造方法 | |
| US6232640B1 (en) | Semiconductor device provided with a field-effect transistor and method of manufacturing the same | |
| JP2002208643A (ja) | 半導体装置の構造およびその製造方法 | |
| JP2002050702A (ja) | 半導体装置 | |
| CN102891109B (zh) | 半导体器件形成方法 | |
| KR20010014923A (ko) | 반도체 장치 및 그 제조 방법 | |
| KR20030060514A (ko) | 삼중 게이트를 갖는 반도체 장치의 제조방법 및 그에 의해제조된 삼중게이트를 가진 반도체 장치 | |
| US7160794B1 (en) | Method of fabricating non-volatile memory | |
| JPH10326896A (ja) | 半導体装置及びその製造方法 | |
| KR100505417B1 (ko) | 반도체소자의 제조방법 | |
| JPH1041505A (ja) | 半導体装置の製造方法 | |
| JPH11251318A (ja) | 半導体装置及びその製造方法 | |
| JPH09298281A (ja) | 半導体装置の製造方法 | |
| KR100506050B1 (ko) | 반도체소자의 콘택 형성방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20031225 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20031225 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040628 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20040831 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041101 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20041130 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050131 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060822 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060824 |
|
| LAPS | Cancellation because of no payment of annual fees |