JP3771843B2 - 導電性接着フィルムを用いるパワー半導体ダイの接着方法 - Google Patents
導電性接着フィルムを用いるパワー半導体ダイの接着方法 Download PDFInfo
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Description
(発明の背景)
本発明は、半導体デバイスに関するものであり、より詳しくは、伝熱性および/または導電性の基板にパワー半導体ダイ(power semiconductor die)を接着させるための新規な方法に関する。
【0002】
ダイオード、MOSFET、IGBTなどのパワー半導体ダイは、通常は、エポキシ樹脂、熱可塑性樹脂、半田などの導電性材料によって、または電気的分離が所望ならば、電気絶縁性材料によって、導電性のリードフレームまたは他の基板に付着される。この方法は、ウェーハからダイをシンギュレーション(singulation)した後に、個々のダイに関して順々に行われるので時間が掛かる。
【0003】
(発明の簡単な説明)
本発明によれば、導電性または電気絶縁性であることができる接着フィルムを、パワー半導体のためのダイ付着材料として用いる。更に、そのような接着フィルムは、ダイシンギュレーション段階前に、パワー半導体ウェーハに付着させる。
【0004】
次に、接着フィルムを用いて、低電力集積回路をリードフレームにボンディングする。本発明によれば、導電性または電気絶縁性の接着フィルムを用いて、パワー半導体を、基板/リードフレームにボンディングする。
【0005】
従来技術における接着フィルムは、プレカットされ、フィルム上にダイを配置する前に基板上に配置される。次に、得られた基板/フィルム/ダイアセンブリは、ダイ/リードフレーム間の接着を向上させるために部分的に熱処理される。本発明によれば、接着フィルムは、ダイシンギュレーション段階前に、パワー半導体ウェーハ上に配置する。次に、ウェーハ/接着フィルムのスタックを、従来のシンギュレーション法を用いて切り分けて、接着フィルムを予め付着したダイを製作する。次に、熱処理により接着剤を再活性化させて、ボンディングを促進し、硬化を完了させる前に、切り分けたダイ/フィルムのスタックを基板/リードフレーム上に配置する。
【0006】
いくつかの利点が本発明によって提供される。すなわち、従来のパワー半導体ダイの付着では、エポキシ樹脂タイプまたは半田タイプの接着剤をペーストまたは液体の形態で使用する。これらの材料は、しばしば、ダイボンディング中に、ダイの縁から基板/リードフレーム上にこぼれる。このこぼれにより、リードフレーム/基板上に配置できるダイのサイズが限定される。接着フィルムを用いることによって、そのようなこぼれがなくなる。その結果、所与のサイズのパッケージ中により大きなダイを配置することができる。ボンド線(bond line)の厚さも、接着フィルムの厚さによって設定され、一定となる。接着剤層中にはボイドも存在しなくなる。
【0007】
ダイシンギュレーション前に、導電性または(電気絶縁性)接着フィルムを、パワー半導体ウェーハ上に予めボンディングすると、組立て中の余計なピックアンドプレイス段階も不要となる。したがって、製造装置のコストが下がり、サイクル時間が短くなる。
【0008】
(発明の実施形態の詳細な説明)
図1および図2は、従来技術のパワー半導体ダイ10と、半田またはエポキシ樹脂の付着材料12によってダイが付着される導電性基板11を示している。従来法では、材料12がこぼれ、それにより、所与の面積の基板上におけるダイの最大サイズが限定されることに留意されたい。
【0009】
図3および図4は、図1および図2のダイ10を示しており、薄くて柔軟な接着フィルム13を用いてダイ10および基板11をボンディングしている。フィルム13は、導電性であるか、または絶縁性であることができ、熱硬化可能である。図3および図4で見られるように、このようなフィルムを用いると、こぼれがなくなるので、図1および図2の基板と同じ面積の基板11上で、より大きな面積のダイ10が可能になる。
【0010】
本発明の新規な方法は、図5から図8に示してある。図5は、従来の方法で同時に加工される多数の同一のパワー半導体ダイを含む半導体デバイスウェーハ21を示している。したがって、ウェーハは、導電性ソース電極および底部導電性ドレイン電極によって従来通り覆われた頂部表面にP/N接合を有する何百もの同一の縦型導電パワーMOSFETダイを含むことができる。ウェーハのダイは、従来の切り分け装置(sawing apparatus)でウェーハを切り分けることによって、シンギュレーションされる。次に、ダイのドレイン電極を基板に半田付けまたはエポキシボンディングすることによって、個々のダイをリードフレームまたは他の基板上に装着する。
【0011】
本発明によれば、接着フィルム20を、約6インチ(15.24cm)の典型的な直径を有することができるウェーハのサイズに切り分ける。
【0012】
フィルム20は、好ましくは、ポリイミドフィルム、例えばPCボードや「フレックス」回路で電気巻線絶縁(electrical winding insulation)など用にしばしば用いられる「KAPTON」(登録商標)フィルムとして公知のポリイミドフィルムである。Kapton(登録商標)ポリイミドは優れた絶縁体である。次に、ウェーハ21およびフィルム20を互いに積層し、予熱して接着力を向上させるが、フィルム20は、完全には硬化させない。
【0013】
次に、図6に概略を示してあるように、フィルム20およびウェーハ21を同時に切り代22で切り分けて、別個のダイにする。従来のフレームまたは基板では、分離したフィルム/ダイのスタックを適所に保持する。次に、シンギュレーションされたデバイスが、自動的に取り上げられ、加熱された各リードフレームまたは基板上の装着すべき場所に運ばれるように、従来のピックアンドプレイスデバイス(pick and place device)中にスタックを配置する。
【0014】
すなわち、図7に示してあるように、従来のピックアンドプレイス装置によって、ダイ/フィルムのスタック21/20を取り上げ、各基板11上に配置することができる。好ましくは、圧力を加えて、予熱された基板11の表面上にスタック21/20を押し付ける。
【0015】
次に、ダイ/フィルムのスタック21/20と基板11を約260℃まで加熱して、フィルム21を完全に熱硬化させ、基板11に対するボンドを形成させる。
【0016】
図7および図8のような構造化を行って、ダイオンダイパッケージ(die−on−die package)(図9)またはサイドバイサイドダイパッケージ(side−by−side die package)(図10)を形成することもできる。すなわち、図9では、接着剤層20と半導体ダイ21とを有する2つの同一のダイ30および31を、ダイ30の上にダイ31を重ねて実装することができる。ダイ30および31は、それぞれ、多種多様なデバイス、例えばMOSFETおよびショットキーダイオードであってもよく、異なるサイズまたは面積であってもよい。あるいは、ダイ31は集積回路であってもよい。
【0017】
さらに、図9における層20は、ダイ30と31とを背面(back−to−back)接続させることのできる、適当な導電性接着フィルムとすることができる。
【0018】
図10に示してあるように、ダイ30および31は、それぞれMOSFETおよびIC(ダイ21)を含んでいてもよい。
【0019】
フィルム20用に使用できる他のフィルムとしては、Alpha Metals 383G(RHS)やUH2W−Eポリイミドフィルム(LHS)などの熱可塑性接着剤ペーストが挙げられる。
【0020】
本発明を、その特定の実施形態に関して説明したが、他の多くの変形形態および改良および他の使用法も当業者には明らかとなるであろう。したがって、本発明は本明細書における具体的な開示によってではなく、添付の特許請求の範囲によってのみ限定されることが好ましい。
【図面の簡単な説明】
【図1】 従来技術のダイ接着の上面図である。
【図2】 従来技術のダイ接着の側面図である。
【図3】 導電性接着フィルムによって基板に接着されたパワー半導体ダイの上面図である。
【図4】 導電性接着フィルムによって基板に接着されたパワー半導体ダイの側面図である。
【図5】 大面積接着フィルムおよび半導体デバイスウェーハのシンギュレーション前の透視図である。
【図6】 接着後の図5の透視図である。
【図7】 基板に接着する前の図6のアセンブリからシンギュレーションされた1つのダイ/フィルムスタックを示す図である。
【図8】 熱硬化およびボンディング後の図8のアセンブリを示す図である。
【図9】 ダイオンダイアセンブリ(die−on−die assembly)に適用される本発明の方法を示す図である。
【図10】 共通基板上におけるダイのサイドバイサイドアセンブリ(side−by−side assembly)に適用される本発明の方法を示す図である。
Claims (11)
- 半導体ダイを基板に接着する方法であって、
まず、第1の面積を有する、薄くて柔軟な熱硬化性でかつポリイミドの絶縁性のフィルムを提供するステップと、
次に、前記第1の面積に比べてそれぞれ実質的に小さい第3の面積を有し、互いに間隔をあけた複数の半導体ダイを提供するような第2の面積を有する半導体ウェーハ上に、剥離シートのない前記薄くて柔軟な熱硬化性フィルムのみを設けるステップと、
次に、前記熱硬化性フィルムと前記半導体ウェーハとを接着するように、前記熱硬化性フィルムを部分的に硬化させるために、前記半導体ウェーハと前記熱硬化性フィルムを予熱するステップと、
次に、個々の素子を形成するために、前記熱硬化性フィルムと前記複数の同一である半導体ダイの両方を同時にシンギュレーションするステップと、
次に、前記基板を加熱するステップと、
次に、前記半導体ダイ上の前記熱硬化性フィルムを前記基板の頂部表面に押し付けて接着するように、前記シンギュレーションされた半導体ダイを前記基板の頂部表面に配置するステップと、
次に、前記熱硬化性フィルムを完全に硬化させて、前記半導体ダイを前記基板に対して堅固に接着させるステップと
を含むことを特徴とする方法。 - 前記基板が、導体リードフレームであることを特徴とする請求項1に記載の方法。
- 前記熱硬化性フィルムが、ポリイミドであることを特徴とする請求項1に記載の方法。
- 前記熱硬化性フィルムが、ポリイミドであることを特徴とする請求項2に記載の方法。
- 前記半導体ダイ上の前記熱硬化性フィルムが、前記基板上での組立て後に、前記半導体ダイの面積と同じ面積を有することを特徴とする請求項1に記載の方法。
- 第2接着フィルムを有する第2半導体ダイを、前記第1半導体ダイから水平方向に移動した位置で前記基板に接着させるステップを含むことを特徴とする請求項1に記載の方法。
- その上に第2接着フィルムを有する第2半導体ダイを、前記基板に固定された前記ダイの頂部に接着させるステップを含むことを特徴とする請求項1に記載の方法。
- 前記第1の面積が、前記第2の面積と実質的に同じであることを特徴とする請求項1に記載の方法。
- 前記半導体ダイおよびフィルムを、ピックアンドプレイス装置によって前記基板へと移動させることを特徴とする請求項1に記載の方法。
- 前記第2接着フィルムが、前記基板に固定される前記半導体ダイの前記頂部表面に比べてより小さい面積を有することを特徴とする請求項7に記載の方法。
- 前記第2半導体ダイと前記第2接着フィルムの両方が、前記基板に固定される前記半導体ダイと同じ面積を有することを特徴とする請求項7に記載の方法。
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PCT/US2000/032176 WO2001039266A1 (en) | 1999-11-24 | 2000-11-22 | Power semiconductor die attach process using conductive adhesive film |
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KR (1) | KR100468233B1 (ja) |
CN (1) | CN1187804C (ja) |
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US6620651B2 (en) | 2001-10-23 | 2003-09-16 | National Starch And Chemical Investment Holding Corporation | Adhesive wafers for die attach application |
US6781352B2 (en) | 2002-12-16 | 2004-08-24 | International Rectifer Corporation | One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter |
KR100885099B1 (ko) * | 2003-12-15 | 2009-02-20 | 후루카와 덴키 고교 가부시키가이샤 | 웨이퍼 가공용 테이프 및 그 제조방법 |
JP2006114649A (ja) * | 2004-10-14 | 2006-04-27 | Fuji Electric Device Technology Co Ltd | 半導体装置の製造方法およびその製造装置 |
CN101807531A (zh) * | 2010-03-30 | 2010-08-18 | 上海凯虹电子有限公司 | 一种超薄芯片的封装方法以及封装体 |
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US5286679A (en) * | 1993-03-18 | 1994-02-15 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer |
JP3467611B2 (ja) * | 1995-09-29 | 2003-11-17 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
US5776799A (en) * | 1996-11-08 | 1998-07-07 | Samsung Electronics Co., Ltd. | Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same |
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KR100468233B1 (ko) | 2005-01-26 |
AU1927501A (en) | 2001-06-04 |
KR20020059782A (ko) | 2002-07-13 |
TW501207B (en) | 2002-09-01 |
CN1399794A (zh) | 2003-02-26 |
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