TW501207B - Power semiconductor die attach process using adhesive film - Google Patents

Power semiconductor die attach process using adhesive film Download PDF

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Publication number
TW501207B
TW501207B TW089124933A TW89124933A TW501207B TW 501207 B TW501207 B TW 501207B TW 089124933 A TW089124933 A TW 089124933A TW 89124933 A TW89124933 A TW 89124933A TW 501207 B TW501207 B TW 501207B
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TW
Taiwan
Prior art keywords
film
die
substrate
scope
patent application
Prior art date
Application number
TW089124933A
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English (en)
Inventor
Mark Paviere
Original Assignee
Int Rectifier Corp
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Publication date
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Publication of TW501207B publication Critical patent/TW501207B/zh

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)

Description

501207 經濟部智慧財產局員工消費合作社印制π A7 _ 1.................... B? --------- 五、發明說明（1). 發明背景 本發明係、關於-半導體裝置且實質地係關於一種功率 半導體晶粒附著至一熱的和/或電的傳導載體之新穎的方 法。 功率半導體晶粒，例如二級體、M0SFETS、IGBTS* 類似物等，一般係藉由電的傳導材料，例如環氧樹脂、熱 塑料、焊料或類似物亦或如果電的絕緣是所欲的時，藉由 電的絕緣材料來附著至傳導引線框或其他基材。從一2圓 單離晶粒後，對於個別的晶粒依序地實施此方法且該方法 是費時的。 發明簡述 關於本發明可能是電的導體或絕緣之黏著膜被使用為 用於功率半導體的晶粒附著材料。此外該黏著膜在該晶粒 單離階段前被附著至功率半導體晶圓。 現在黏著膜被用來黏結低功率積體電路至引線框。關 於本發明，電的導體或絕緣黏著膜被用來黏結功率半導體 至基材/引線框。 在習知技藝中黏著膜是預切的且在晶粒放置於該膜上 之刖被放置在基材上。該合成基材/膜/晶粒總成因此部分 地被熱處理以促進晶粒/引線框架之間的黏著。關於本發 明，該黏著膜在該晶粒單離階段前被放置在該功率半導體 晶圓上。隨後使用習知的單離方法鋸開該晶圓/黏著膜疊 塊，製成具有預先附著該黏著膜的晶粒。在經由熱處理重 覆活化該黏著以促進黏結和完成該固化之前，該被鋸開的 本紙張尺度剌中Κ國家標準（CNS)A4規格（2〗ϋχ297公爱）
------I -------^ (請先A3讀背面之注意事項再填寫本頁) 4 發明說明（2) 晶粒/薄膜疊塊被放置在一基材/引線框上。 藉由本發明將提供一些利益。因而，傳統的功率半導 體晶粒附著涉及使用以糊料或液體形式的環氧樹脂或焊料 型黏著劑。在晶粒黏結過程中這些材料通常從該晶粒的邊 緣溢出至該基材/引線框上。此溢出限制了晶粒可以被放 置在該引線框/基材上的大小。藉由使用一黏著膜來消除 這樣的溢出。較大的晶粒可以隨後被放置在一被給予大小 的一封裝體上0黏結線厚度也藉由該黏著膜厚度被設定且 成為常態。也將沒有空隙在該黏結中。 於晶粒單離之前預先黏結電的導體（或電的絕緣）黏著 膜至該功率半導體晶圓上，也在總成過程中移除一多的拾 起及放置步驟之需求。製造設備成本和循環時間也因此減 少。 圓式簡要說明 第1圖和第2圖係分別為一習知技藝晶粒附著的頂視圖 和側視圖； 第3圖和第4圖係分別為一功率半導體晶粒藉由一導體 黏著膜附著至一基材的頂視圖和側視圖； 第5圖為一大區域黏著膜和一半導體裝置晶圓在單離 之前的立體圖； 第6圖為第5圖在黏著之後的立體圖； 第7圖顯示-晶粒薄膜疊塊在附著至—基材之前從第6 圖的總成單離。 第8圖顯示在熱固化和黏結後之第7圖的總 501207 Λ7 ____ Β7 五、發明說明（3) 第9圖顯示本發明應用至一晶粒疊晶粒總成上的方 法。 (請先閱讀背面之注意事項再填寫本頁) 第10圖顯示本發明應用至一並肩晶粒總成在--般基 材上的方法。 本發明具艘實施例之詳細描述 第1和第2圖顯示一習知功率半導體晶粒1 〇和藉由一焊 料或環氧樹脂附著材料12被附著的一傳導性基材11。要注 意的是該材料12—般都會溢出，因此限制該晶粒在一被給 予區域之基材上的最大尺寸。 第3圖和第4圖顯示第1圖和第2圖之該晶粒，其中一個 薄且具有可撓性的黏著膜13被用來黏結該晶粒1 〇和該基材 11。該膜13為電的導體或可能是絕緣的且是熱固化的。可 以在第3圖和第4圖中看到使用這種膜來消除溢出，因此使 得一較大區域的晶粒10在如第1和第2圖中相同區域的基材 11上。 經濟部智慧財產局員工消費合作社印制取 本發明新穎的方法顯示在第5圖至第8圖上。第5圖顯 示一半導體裝置晶圓21，其包含許多相同的功率半導體晶 粒’該等晶粒同時地被處理在一習知的方法中。因此，該 晶圓可以包含許多相同的垂直傳導功率MOSFET晶粒，該 專晶粒有Ρ/Ν接合點在其等之頂表面，一般係藉由一傳導 源電極和一底部傳導外流電極被覆蓋。該晶圓的晶粒藉由 使用習知的鋸開裝置來鋸開該晶圓而被單離。該個別的晶 粒藉由焊接或環氧樹脂黏結該晶粒的該外流電極至該基材 而隨後被安裝在一引線框架或其他基材上。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） 6 501207
經濟部智慧財產局員工消費合作社印制农 五、發明說明（4) 關於本發明，一黏著膜20被切割成該晶圓的尺寸，該 晶圓可以有一般大約為6吋的直徑。 膜20較佳為一聚醯亞胺膜例如所知為一”kapton，， 膜’其通常使用在用於電氣捲曲絕緣和類似物的PC板、” 撓曲’’電路上。該Kapton聚醯亞胺是一種極好的絕緣體。 隨後該膜2 0相互躺在該晶圓21的頂部且被預先加熱以促進 黏著但不完全固化該膜20。 其後如圖解顯示在第6圖，該膜20和該晶圓21在 切割線22被同時地鋸開成分離的晶粒。一習知的框架或載 體保持該分離的膜/晶粒疊塊在定位且該疊塊隨後被放置 在一習知的拾·放裝置以致於該單離裝置可以被拾起且被 搬運至一定位，在一自動化的方式中該位置被安裝在個別 的加熱引線框或基材上。 因此，如第7圖所示，該晶粒/膜疊塊21/20可以 用一習知的拾-放裝置被拾起且被放置在一個別基材的頂 部。較佳地壓力用於壓縮該疊塊21/20至該預熱基材11的 表面上。 其後，該晶粒/膜疊塊21/20和該基材11被加熱至 大約26〇t：而完全地加熱固化膜21以對該基材11形成一黏 結。 也可以實行第7圖和第8圖的結構以形成晶粒疊晶 粒封裝體（第9圖）或並排晶粒封裝體（第10圖）。因此， 在第9圖，有黏著層20和半導體晶粒21的兩個相同晶 粒30和31可能被安裝成晶粒31在晶粒30的頂部。晶粒 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） I -----·1111111 ^ ·11111111 (請先閱讀背面之注意事項再填寫本頁) 7 501207 .經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（》· 30和31可能是不同種類的裝置，例如，分別為一 MOSFET和一肖特基二極體且可能是不同大小的區 域。可擇地，晶粒31可以是一積體電路。 此外，在第9圖的膜20可以是適於電的導體 黏著膜以讓晶粒30和31背對背相連。 如第10圖所示，該晶粒30和31分別包括一 MOSFET和一 1C(晶粒 21)。 可以被用於膜20的其他膜包括熱塑性黏著糊料例 如α金屬383G(RHS)和UH2W-E聚醯亞胺膜（LHS)。 雖然本發明已描述在關於其個別的具體實施例 中對於熟知此技藝者許多其他的變化和修正及其他使用 將變得顯而易見的。因此，較佳為本發明將不限於這裡所 特別揭露的但只限於該附加的申請專利範圍。 -----I ---1#I I ·!ΙΙ — — — — ^ ·1111111· (請先閱讀背面之注意事項再填寫本頁) 元件標號對照表 10 功率半導體晶粒 11 傳導性基材 12 焊料或環氧樹脂附著材料 13 黏著膜 20 黏著膜 21 半導體裝置晶圓 22 切割線 30 晶粒 31 晶粒

Claims (1)

  1. 六、申請專利範圍 L 一種連接半導體晶粒至一基材的一種方法·· 該方法包括黏著一個薄且具可撓性之可熱固化獏 至為第一區域之薄半導體晶圓的步驟，該膜至少部 分地被固化且具有一第一區域，以及該薄半導體晶圓 1、有第一區域，該第二區域含有多個側向移置的相 同半導體晶粒，該等半導體晶粒個自地具有第三區 域該第二區域係各別地實質小於該第一區域的區 域； 其後同時地單離該可熱固化膜和該等相同的晶 粒’以形成個別的元件，各個該等元件具有該晶粒之 區域和一被黏著至該晶粒之一表面之黏著膜的配合區 域； 其後將該經單離的晶粒施放至該基材表面之頂 面，且位在該晶粒上之該膜壓抵該頂面；以及 其後完全地固化該膜，以穩固地黏著該晶粒至該 基材。 2·如申請專利範圍第！項之方法，其中該基材為一導體 引線框。 3·如申請專利範圍第旧之方法，其中該膜為一聚酿亞 4. 如申請專利範圍第2項之方法，其中該膜為一聚酿亞 胺。 5. 如申請專利範圍第旧之方法，其中位在該晶粒上之 該膜於組合至該基材之後具有相同於該晶粒的區域。 本^•張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐 -9 - 六、申請專利範圍 7. 如申請專利範圍第】項之方法，其包括另一步驟：將 -具有-第二黏著膜於其上的第二半導體晶粒黏著至 被固定於該基材上之晶粒的頂部。 如申請專利範圍第!項之方法，其中該第一區域實質 相同於該第二區域。 11·如申請專利範圍第7項之方法 其中該晶粒和該骐藉
    本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 6. ”請專利範圍第1項之方法，其包括另-步驟：在 一從該第一晶粒側向移離的位置處，將一具有—第二 黏著膜於其上的第二半導體晶粒黏著至該基材上。 9·如申請專利範圍第1項之方法 由拾-放裝置被移動至該基材。 訂 10·如申請專利範圍第1項之方法 小於該晶粒之頂表面的區域。 小於該晶粒之頂表面的區域，且其中該第二晶粒㈣ 第-黏者膜兩者具有相同於該黏著膜的區域。
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US6620651B2 (en) * 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US6781352B2 (en) 2002-12-16 2004-08-24 International Rectifer Corporation One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter
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US5286679A (en) * 1993-03-18 1994-02-15 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer
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