CN1399794A - 采用导电的粘合膜的功率半导体管芯的连接方法 - Google Patents

采用导电的粘合膜的功率半导体管芯的连接方法 Download PDF

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CN1399794A
CN1399794A CN00816153A CN00816153A CN1399794A CN 1399794 A CN1399794 A CN 1399794A CN 00816153 A CN00816153 A CN 00816153A CN 00816153 A CN00816153 A CN 00816153A CN 1399794 A CN1399794 A CN 1399794A
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tube core
bonding film
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M·帕维尔
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Infineon science and technology Americas
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Abstract

一个大面积的粘合膜(20)被连接到包含有大量相同结构的半导体晶片(21)上。然后，粘合膜(20)和晶片(21)被同时切割且其上带有粘合膜的单个的管芯接着被放置到一个引线框架上，粘合膜被完全固化，以将半导体管芯粘合到引线框架上。多个管芯能够被并排被安装在一个共同的衬底上(11)，或者一个管芯能够被安装在已经位于衬底(11)上的另一个管芯上。

Description

采用导电的粘合膜的功率半导体管芯的连接方法
发明背景
本发明涉及半导体器件，尤其涉及一种用于将功率半导体管芯连接到导热和/或导电的支承体上的新方法。
功率半导体管芯例如二极管、MOSEFT(金属-氧化物-半导体场效应晶体管)和IGBT(集成门双极型晶体管)等一般是通过导电材料(例如环氧树脂、热塑性塑料和焊料等)连接到导电引线框架或其他衬底上，如果需要电绝缘，则使用电绝缘材料进行连接。该方法是在将晶片分割成管芯后应用于单个的管芯，并且非常耗时。
发明简介
根据本发明，可以是导电或绝缘的粘合膜被用作功率半导体的管芯连接材料。此外，在管芯分割阶段之前，该种粘合膜便被连接功率半导体晶片上。
粘合膜现在被用于将低功率集成电路接合到引线框架上。根据本发明，导电或绝缘的粘合膜被用于将功率半导体接合到衬底/引线框架上。
现有技术的粘合膜在管芯被置于其上之前被预先切割并被置于衬底上。然后，得到的衬底/粘合膜/管芯的组件被部分热处理，以促进管芯和引线框架之间的粘合。根据本发明，在管芯分割阶段之前，粘合膜被放到功率半导体晶片上。然后，利用传统的分割方法将晶片/粘合膜的叠层体进行锯开，形成带有预先连接的粘合膜的管芯。接着，在为了促进接合及完成固化而利用热处理重新活化粘合膜之前，经锯切得到的管芯/粘合膜叠层体被放到一个衬底/引线框架上。
利用本发明可以带来多种好处。例如，通常的功率半导体管芯的连接使用糊状或液体状的环氧树脂或焊料类粘合剂。这些材料在管芯接合的过程中，经常会从管芯的边缘溢出到衬底/引线框架上。这种溢出限制了能被放到引线框架/衬底上的管芯的尺寸。而通过使用一层粘合膜，则可以避免这种溢出。这样，更大的管芯就能够被放到给定尺寸的封装中。接合线的厚度也由粘合膜的厚度决定，且为常数。接合中的空隙也会被消除。
在管芯分割之前，将导电的或电绝缘的粘合膜预先接合到功率半导体晶片上，也可以省去组装中需要的额外的拾取和放置阶段。从而制造成本会降低，制造周期会缩短。
附图简要描述
图1和图2分别是现有技术中管芯连接的俯视图和侧视图。
图3和图4分别是功率半导体管芯通过导电的粘合膜连接到衬底的俯视图和侧视图。
图5是一个大面积的粘合膜和一个半导体器件晶片在分割之前的透视图。
图6是图5中的内容在粘结后的透视图。
图7示出了一个由图6所示组件上分割出的一块管芯/粘合膜叠层体在被连接到衬底之前的情况。
图8示出了经过热固化和接合后的图7中的组件。
图9示出了本发明方法用于层叠的管芯组件的情况。
图10示出了本发明方法被用于在一个共同衬底上并排排列的管芯组件的情况。
本发明实施例的详细描述
图1和图2示出了一个现有技术的功率半导体管芯10和一个传导性衬底11，他们之间通过焊料或环氧树脂等连接材料12连接。注意，材料12通常会溢出，这会限制给定大小的衬底上的管芯的最大尺寸。
图3和图4示出了图1和图2中的管芯10，其中采用了一层薄而柔性的粘合膜13接合管芯10和衬底11。粘合膜13可以是导电的，也可以是绝缘的，并且是热固性的。如图3和图4所示，采用该粘合膜可以消除了粘合剂的溢出，从而可以在与图1和图2所示的同样面积的衬底11上连接更大面积的管芯10。
本发明的新方法如图5至图8所示。图5示出了一个半导体器件晶片21，晶片包括大量以传统方法同时加工出的相同的功率半导体管芯。这样，该晶片上可以包括很多顶部表面带有P/N结的同样的垂直传导的功率MOSFET管芯，管芯通常覆盖有一个导电源电极和一个底部导电漏电极。晶片的管芯是利用使用传统的锯切装置通过锯开晶片而分割成的。然后，通过用焊料或环氧树脂将管芯的漏极接合到衬底上，单个的管芯被安装在引线框架或其他衬底上。
根据本发明，粘合膜20被切割成品片的尺寸，其具有通常的约6英寸的直径。
粘合膜20优选地是聚酰亚胺膜，例如一种已知经常用于PC板、“花线”电路中实现电绕组绝缘或类似功能的“KAPTON”膜。KAPTON聚酰亚胺是一种优秀的绝缘体。然后，晶片21和粘合膜20被层叠地放置，并经过预先加热处理，以提高粘性，但不完全固化粘合膜20。
在此之后，如图6所示，粘合膜20和晶片21被按照切割线22同时锯切成单个的管芯。一个通常的框架或支座支持这些单个的粘合膜/管芯叠层体，然后这些叠层体被放置到通常的拾取和放置设备中，以便这些被分割出的器件能够自动被拾取以及运送到各自被加热的引线框架或衬底上要安装的位置。
于是，如图7所示，管芯/粘合膜叠层体21/20可以利用通常的拾取和放置设备拾取并放置到相应的衬底11上。最好施加压力以将21/20叠层体压到预先加热过的衬底11的表面上。
之后，管芯/粘合膜叠层体21/20和衬底11被加热到大约260℃以对粘合膜21进行完全的热固化，形成与衬底11的接合。
图7和图8所示的结构也可被用于形成图9所示的层叠管芯封装或图10所示的并排放置的管芯。这样，在图9中，两个带有粘合层20和半导体管芯21的同样的管芯30和31就可以被安装成管芯31位于管芯30之上。管芯30和管芯31可以是不同的器件，例如分别是一个MOESFET和一个肖特基二极管，也可以有不同的尺寸或面积。另外，管芯31也可以是一块集成电路。
除此之外，图9中的粘合层20也可以是一种适当的导电的粘合膜，以允许管芯30和管芯31背对背连接。
如图10所示，管芯30和管芯31可以分别包含一个MOSFET和一个集成电路(管芯21)。
可用于粘合膜20的其它材料包括热塑性塑料粘合胶，例如阿尔法金属383G(RHS)和UH2W-E聚酰亚胺膜(LHS)。
虽然本发明已用具体的实施例进行了描述，但许多其他的变形或改进以及其他的应用对本领域的技术人员是显而易见的。因此，本发明不受这里给出的具体内容的限定，而只由所附的权利要求书限定。

Claims (11)

1、将半导体管芯连接到衬底上的方法，所述方法包括如下步骤：将一层至少部分地热固化且具有第一面积的薄的、柔性的、热固性的膜粘合到具有第二面积的薄的半导体晶片上，半导体晶片包含多个并排放置的具有各自第三面积的同样的半导体管芯，每个第三面积比所述第一面积小很多；
之后，同时分割所述热固性的粘合膜和所述多个同样的管芯，以形成单个的元件，每个元件具有所述管芯的面积和粘合到所述管芯的一个表面的匹配的粘合膜的面积；
之后，将所述分割得到的管芯放到所述衬底的上表面，并使所述管芯上的粘合膜压在所述上表面上；
之后，完全固化所述粘合膜，以使所述管芯牢固地粘附在所述衬底上。
2、如权利要求1所述的方法，其特征在于，所述衬底是导体引线框架。
3、如权利要求1所述的方法，其特征在于，所述粘合膜是聚酰亚胺。
4、如权利要求2所述的方法，其特征在于，所述粘合膜是聚酰亚胺。
5、如权利要求1所述的方法，其特征在于，所述位于所述管芯上的粘合膜在安装到所述衬底上后，具有与所述管芯相同的面积。
6、如权利要求1所述的方法，包括下述进一步的步骤：将其上带有第二粘合膜的第二半导体管芯在与所述第一管芯横向分开的位置粘合到所述衬底上。
7、如权利要求1所述的方法，包括下述进一步的步骤：将其上带有第二粘合膜的第二管芯粘合在被固定到所述衬底上的所述管芯的顶部。
8、如权利要求1所述的方法，其特征在于，所述第一面积与所述第二面积大致相同。
9、如权利要求1所述的方法，其特征在于，所述管芯和粘合膜通过拾取和移动设备被移动到所述衬底上。
10、如权利要求1所述的方法，其特征在于，所述粘合膜具有比所述管芯的所述顶面小的面积。
11、如权利要求7所述的方法，其特征在于，所述粘合膜具有比所述管芯的所述顶面小的面积并且所述第二管芯和所述第二粘合膜均具有与所述粘合膜相同的面积。
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CN100463114C (zh) * 2003-12-15 2009-02-18 古河电气工业株式会社 晶片加工带及其制造方法
CN101807531A (zh) * 2010-03-30 2010-08-18 上海凯虹电子有限公司 一种超薄芯片的封装方法以及封装体

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US6620651B2 (en) 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US6781352B2 (en) 2002-12-16 2004-08-24 International Rectifer Corporation One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter
JP2006114649A (ja) * 2004-10-14 2006-04-27 Fuji Electric Device Technology Co Ltd 半導体装置の製造方法およびその製造装置

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JP2994510B2 (ja) * 1992-02-10 1999-12-27 ローム株式会社 半導体装置およびその製法
US5286679A (en) * 1993-03-18 1994-02-15 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer
JP3467611B2 (ja) * 1995-09-29 2003-11-17 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
US5776799A (en) * 1996-11-08 1998-07-07 Samsung Electronics Co., Ltd. Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same

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CN100463114C (zh) * 2003-12-15 2009-02-18 古河电气工业株式会社 晶片加工带及其制造方法
CN101807531A (zh) * 2010-03-30 2010-08-18 上海凯虹电子有限公司 一种超薄芯片的封装方法以及封装体

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