WO2001039266A1 - Power semiconductor die attach process using conductive adhesive film - Google Patents
Power semiconductor die attach process using conductive adhesive film Download PDFInfo
- Publication number
- WO2001039266A1 WO2001039266A1 PCT/US2000/032176 US0032176W WO0139266A1 WO 2001039266 A1 WO2001039266 A1 WO 2001039266A1 US 0032176 W US0032176 W US 0032176W WO 0139266 A1 WO0139266 A1 WO 0139266A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- die
- film
- substrate
- area
- adhesive film
- Prior art date
Links
- 239000002313 adhesive film Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000000034 method Methods 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 13
- 239000000463 material Substances 0.000 description 5
- 239000004593 Epoxy Substances 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
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- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
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Definitions
- This invention relates to semiconductor devices and more specifically relates to a novel process for the attachment of power semiconductor die to a thermally and/or electrically conductive support.
- Power semiconductor die such as diodes, MOSFETs, IGBTs and the like are normally attached to conductive lead frames or other substrates by electrically conducting materials such as epoxies, thermoplastics, solders and the like or by electrically insulative materials if electrical isolation is desired. This process is carried out sequentially for individual die, after die singulation from a wafer and is time consuming.
- adhesive films which may be electrically conductive or insulative are used as the die attach material for power semiconductors. Further, such adhesive films are attached to power semiconductor wafers before the die singulation stage.
- Adhesive films are now used to bond low power integrated circuits to lead frames.
- electrically conductive or insulative adhesive films are used to bond power semiconductors to substrates/lead frames.
- Adhesive films in the prior art are pre-cut and placed onto a substrate before the placement of die on the film.
- the resultant substrate/film/die assembly is then partially heat treated to promote adhesion between die/lead frame.
- the adhesive film is placed onto the power semiconductor wafer before the die singulation stage.
- the wafer/adhesive film stack is then sawn using conventional singulation methods, producing die with the adhesive film pre-attached.
- the sawn die/film stack is then placed onto a substrate/lead frame before re-activating the adhesive via heat treatment to promote bonding and complete the curing.
- conventional power semiconductor die attach involves use of epoxy or solder type adhesives in paste or liquid form. These materials often overspill from the edge of the die onto the substrate/lead frame during die bonding. This overspill limits the size of die that can be placed on the lead frame/substrate. By using an adhesive film, such overspill is eliminated. Larger die can then be placed in a package of a given size. Bond line thickness is also set by the adhesive film thickness and will be constant. Voids in the bond will also be absent.
- Pre-bonding electrically conductive or (electrically isolating) adhesive film onto the power semiconductor wafer before die singulation also removes the requirement of an extra pick and place stage during assembly. Manufacturing equipment costs and cycle times are therefore reduced.
- Figure 1 and 2 are top and side views respectively of a prior art die attach.
- Figure 3 and 4 are top and side views respectively of a power semiconductor die attached to a substrate by a conductive adhesive film.
- Figure 5 is a perspective diagram of a large area adhesive film and a semiconductor device wafer before singulation.
- Figure 6 is a perspective diagram of Figure 5 after adhesion.
- Figure 7 shows one die/film stack singulated from the assembly of Figure 6 before attachment to a substrate.
- Figure 8 shows the assembly of Figure 8 after heat cure and bonding.
- Figure 9 shows the process of the invention as applied to a die-on-die assembly.
- Figure 10 shows the process of the invention as applied to a side-by - side assembly of die on a common substrate.
- Figures 1 and 2 show a prior art power semiconductor die 10 and a conductive substrate 11 to which it is attached by a solder or epoxy attach material 12. Note that material 12 conventionally overspills, thereby limiting the maximum size of the die on a substrate of given area.
- Figure 3 and 4 show the die 10 of Figures 1 and 2 where a thin, flexible adhesive film 13 is used to bond the die 10 and substrate 11.
- Film 13 is electrically conductive or may be insulative, and is heat curable. The use of such film is seen in Figures 3 and 4 to eliminate overspill, thus enabling a larger area die 10 on the substrate 11 of same area as that of Figures 1 and 2.
- Figure 5 shows a semiconductor device wafer 21 which contains a large number of identical power semiconductor die which are simultaneously processed in a conventional manner.
- the wafer can contain hundreds of identical vertical conduction power MOSFET die which have P/N junctions in their top surface, conventionally covered by a conductive source electrode and a bottom conductive drain electrode.
- the die of the wafer are singulated by sawing the wafer with conventional sawing apparatus.
- the individual die are then to be mounted on a lead frame or other substrate by soldering or epoxy bonding the drain electrode of the die to the substrate.
- an adhesive film 20 is cut to the size of the wafer, which can have a typical diameter of about 6 inches.
- Film 20 is preferably a polyimide film such as that know as a "KAPTON” film which is frequently used in PC boards, "flex” circuits, for electrical winding insulation and the like.
- the Kapton polyimide is an excellent insulator.
- the wafer 21 and film 20 are then laid atop one another and are preheated to promote adhesion, but to not fully cure the film 20.
- the film 20 and wafer 21 are simultaneously sawn at cut lines 22 into separate die.
- a conventional frame or support keeps the separated film/die stacks in place and the stacks are then placed into a conventional pick and place device so that the singulated devices can be picked up and carried to a location to be mounted on respective heated lead frames or substrates in an automated manner.
- the die/film stack 21/20 can be picked up and placed atop a respective substrate 11 with a conventional pick and place apparatus. Pressure is preferably applied to press the stack 21/20 onto the surface of the pre-heated substrate 11.
- the die/film stack 21/20 and substrate 11 are heated to about 260 °C to fully heat cure film 21 to form a bond to the substrate 11.
- FIG. 7 The structure of figures 7 and 8 can also be carried out to form die-on- die packages ( Figure 9) or side-by-side die packages ( Figure 10).
- Figure 9 die-on- die packages
- Figure 10 side-by-side die packages
- die 30 and 31 having adhesive layers 20 and semiconductor die 21 may be mounted with die 31 atop die 30.
- Die 30 and 31 may be diverse devices, for example, a MOSFET and a Schottky diode respectively and may be of different sizes or areas.
- die 31 can be an integrated circuit.
- layers 20 in Figure 9 can be a suitable electrically conductive adhesive film to allow back-to-back connection of die 30 and 31.
- the die 30 and 31 may contain a MOSFET and an IC respectively (die 21).
- thermoplastic adhesive paste such as Alpha Metals 383G (RHS) and UH2W-E polyimide film
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001540836A JP3771843B2 (en) | 1999-11-24 | 2000-11-22 | Power semiconductor die bonding method using conductive adhesive film |
AU19275/01A AU1927501A (en) | 1999-11-24 | 2000-11-22 | Power semiconductor die attach process using conductive adhesive film |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16745699P | 1999-11-24 | 1999-11-24 | |
US60/167,456 | 1999-11-24 |
Publications (2)
Publication Number | Publication Date |
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WO2001039266A1 true WO2001039266A1 (en) | 2001-05-31 |
WO2001039266A9 WO2001039266A9 (en) | 2002-04-18 |
Family
ID=22607438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/032176 WO2001039266A1 (en) | 1999-11-24 | 2000-11-22 | Power semiconductor die attach process using conductive adhesive film |
Country Status (6)
Country | Link |
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JP (1) | JP3771843B2 (en) |
KR (1) | KR100468233B1 (en) |
CN (1) | CN1187804C (en) |
AU (1) | AU1927501A (en) |
TW (1) | TW501207B (en) |
WO (1) | WO2001039266A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6620651B2 (en) | 2001-10-23 | 2003-09-16 | National Starch And Chemical Investment Holding Corporation | Adhesive wafers for die attach application |
US6781352B2 (en) | 2002-12-16 | 2004-08-24 | International Rectifer Corporation | One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100463114C (en) * | 2003-12-15 | 2009-02-18 | 古河电气工业株式会社 | Tape for wafer processing and manufacturing method thereof |
JP2006114649A (en) * | 2004-10-14 | 2006-04-27 | Fuji Electric Device Technology Co Ltd | Method and apparatus for manufacturing semiconductor device |
CN101807531A (en) * | 2010-03-30 | 2010-08-18 | 上海凯虹电子有限公司 | Ultra-thin chip packaging method and packaged body |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5286679A (en) * | 1993-03-18 | 1994-02-15 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer |
US5411921A (en) * | 1992-02-10 | 1995-05-02 | Rohm Co., Ltd. | Semiconductor chip die bonding using a double-sided adhesive tape |
US5776799A (en) * | 1996-11-08 | 1998-07-07 | Samsung Electronics Co., Ltd. | Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same |
US5960260A (en) * | 1995-09-29 | 1999-09-28 | Texas Instruments Incorporated | Semiconductor device, its manufacturing method, and dicing adhesive element therefor |
-
2000
- 2000-11-22 JP JP2001540836A patent/JP3771843B2/en not_active Expired - Fee Related
- 2000-11-22 AU AU19275/01A patent/AU1927501A/en not_active Abandoned
- 2000-11-22 CN CNB008161534A patent/CN1187804C/en not_active Expired - Fee Related
- 2000-11-22 KR KR10-2002-7006634A patent/KR100468233B1/en not_active IP Right Cessation
- 2000-11-22 WO PCT/US2000/032176 patent/WO2001039266A1/en active IP Right Grant
- 2000-11-23 TW TW089124933A patent/TW501207B/en active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5411921A (en) * | 1992-02-10 | 1995-05-02 | Rohm Co., Ltd. | Semiconductor chip die bonding using a double-sided adhesive tape |
US5286679A (en) * | 1993-03-18 | 1994-02-15 | Micron Technology, Inc. | Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer |
US5960260A (en) * | 1995-09-29 | 1999-09-28 | Texas Instruments Incorporated | Semiconductor device, its manufacturing method, and dicing adhesive element therefor |
US5776799A (en) * | 1996-11-08 | 1998-07-07 | Samsung Electronics Co., Ltd. | Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6620651B2 (en) | 2001-10-23 | 2003-09-16 | National Starch And Chemical Investment Holding Corporation | Adhesive wafers for die attach application |
CN1303660C (en) * | 2001-10-23 | 2007-03-07 | 国家淀粉及化学投资控股公司 | Adhesive wafers for die attach application |
US6781352B2 (en) | 2002-12-16 | 2004-08-24 | International Rectifer Corporation | One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter |
Also Published As
Publication number | Publication date |
---|---|
JP2003515929A (en) | 2003-05-07 |
TW501207B (en) | 2002-09-01 |
WO2001039266A9 (en) | 2002-04-18 |
AU1927501A (en) | 2001-06-04 |
CN1187804C (en) | 2005-02-02 |
CN1399794A (en) | 2003-02-26 |
KR100468233B1 (en) | 2005-01-26 |
JP3771843B2 (en) | 2006-04-26 |
KR20020059782A (en) | 2002-07-13 |
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