JP2003007913A - Method of manufacturing semiconductor device and semiconductor module - Google Patents

Method of manufacturing semiconductor device and semiconductor module

Info

Publication number
JP2003007913A
JP2003007913A JP2001193042A JP2001193042A JP2003007913A JP 2003007913 A JP2003007913 A JP 2003007913A JP 2001193042 A JP2001193042 A JP 2001193042A JP 2001193042 A JP2001193042 A JP 2001193042A JP 2003007913 A JP2003007913 A JP 2003007913A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor
terminal
wiring
semiconductor module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001193042A
Other languages
Japanese (ja)
Other versions
JP4656766B2 (en
JP2003007913A5 (en
Inventor
Masakuni Shibamoto
正訓 柴本
Kazunari Suzuki
一成 鈴木
Yoshinori Miyaki
美典 宮木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Priority to JP2001193042A priority Critical patent/JP4656766B2/en
Publication of JP2003007913A publication Critical patent/JP2003007913A/en
Publication of JP2003007913A5 publication Critical patent/JP2003007913A5/ja
Application granted granted Critical
Publication of JP4656766B2 publication Critical patent/JP4656766B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

PROBLEM TO BE SOLVED: To prevent degradation in the reliability of a semiconductor device or a semiconductor module due to the warpage of a wiring board (carrier material), and to reduce an assembly failure due to the warpage of the wiring board (carrier material). SOLUTION: The wiring board (carrier material) is bonded onto a supporting plane by bonding whose adhesive power is strong and whose peeling is easy. A plurality of semiconductor elements or semiconductor modules (chips) are loaded in prescribed positions on the upper face of the wiring board. The outer terminal (pad) of the semiconductor element and a wiring terminal are electrically connected by an electric connection material. The semiconductor element, the electric connection material and a connection part where the outer terminal and the wiring terminal are electrically connected are mold-sealed by resin and the like. The wiring board is peeled from the supporting plane and a terminal for outer device connection is formed in the outer terminal of the semiconductor module at the back of the peeled wiring board. The device including the respective semiconductor elements or the semiconductor module elements is separated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置もしく
は半導体モジュールの製造方法に関し、特に、ボール・
グリド・アレイ(BGA)型パッケージ、ランド・グリ
ッド・アレイ(LGA)型パッケージに適用して有効な
技術に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device or a semiconductor module, and more particularly to a ball
The present invention relates to a technique effectively applied to a grid array (BGA) type package and a land grid array (LGA) type package.

【0002】[0002]

【従来の技術】従来、薄いBGA型パッケージあるいは
LGA型パッケージを用いた半導体装置もしくは半導体
モジュールは、薄い配線基板の上面の所定位置に多数個
の半導体素子もしくは半導体モジュール(チップ)を搭
載し、前記半導体素子もしくは半導体モジュールの外部
端子(パッド)と配線端子とをワイヤで電気的に接続
し、この状態で前記半導体素子もしくは半導体モジュー
ル、ワイヤ、及び前記外部端子(パッド)と配線端子と
が電気的に接続された部分を樹脂でモールド封止し、前
記配線基板上の各半導体素子もしくは半導体モジュール
をダイシングしてそれぞれを分離し、この分離された各
半導体素子もしくは半導体モジュールに金属ボール等の
外部装置接続用端子を形成して製造されている。
2. Description of the Related Art Conventionally, a semiconductor device or a semiconductor module using a thin BGA type package or an LGA type package has a large number of semiconductor elements or semiconductor modules (chips) mounted at predetermined positions on the upper surface of a thin wiring board. The external terminals (pads) of the semiconductor element or the semiconductor module are electrically connected to the wiring terminals by wires, and in this state, the semiconductor element or the semiconductor module, the wires, and the external terminals (pads) and the wiring terminals are electrically connected. The portion connected to is molded and sealed with resin, and each semiconductor element or semiconductor module on the wiring board is diced to be separated, and each separated semiconductor element or semiconductor module is provided with an external device such as a metal ball. It is manufactured by forming connection terminals.

【0003】[0003]

【発明が解決しようとする課題】本発明者は、前記従来
技術を検討した結果、以下の問題点を見いだした。配線
基板として薄い基板あるいはフィルムを用いると、薄い
半導体装置もしくは半導体モジュール全体の剛性が低
く、かつ、ペレット付け、ワイヤボンディング、樹脂モ
ールド等の組み立て時の熱履歴及び異なる材料の線膨張
係数の差により、配線基板(キャリア材)が大きく変形
するという問題があった。また、多数の半導体素子もし
くは半導体モジュールを薄い配線基板に搭載すると、前
記配線基板の面積が大きくなり、反りを助長するという
問題があった。また、前記薄い配線基板の反りにより、
組立時の位置精度が低下し、ボイドによる接着不良(導
電不良)、搬送工程におけるトラブルによる不良等が増
加して、半導体装置もしくは半導体モジュールの信頼性
が低下するという問題があった。
The present inventor has found the following problems as a result of examining the above-mentioned prior art. When a thin substrate or film is used as the wiring board, the rigidity of the thin semiconductor device or semiconductor module as a whole is low, and due to the thermal history during assembly such as pelleting, wire bonding, resin molding, and the difference in the linear expansion coefficient of different materials. However, there is a problem that the wiring board (carrier material) is largely deformed. Further, when a large number of semiconductor elements or semiconductor modules are mounted on a thin wiring board, the area of the wiring board becomes large, and there is a problem that warpage is promoted. Also, due to the warp of the thin wiring board,
There is a problem in that the positional accuracy during assembly is reduced, adhesion defects (conduction defects) due to voids, defects due to troubles in the transfer process, and the like increase, and the reliability of the semiconductor device or semiconductor module decreases.

【0004】本発明の目的は、薄い配線基板(キャリア
材)の反りによる半導体装置の信頼性の低下を防止する
ことが可能な技術を提供することにある。本発明の他の
目的は、配線基板(キャリア材)の反りによる組み立て
不良を低減することが可能な技術を提供することにあ
る。本発明の前記ならびにその他の目的と新規な特徴
は、本明細書の記述及び添付図面によって明らかになる
であろう。
An object of the present invention is to provide a technique capable of preventing deterioration of reliability of a semiconductor device due to warpage of a thin wiring board (carrier material). Another object of the present invention is to provide a technique capable of reducing defective assembly due to warpage of a wiring board (carrier material). The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

【0005】[0005]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。すなわち、本発明は、支持用平板
の上に、接着力が強くかつ剥離が容易な接着材で、多数
素子搭載用配線があらかじめ設けられている配線基板を
貼り付け、その配線基板の上面の所定位置に複数個の半
導体素子(チップ)を搭載し、前記半導体素子の外部端
子(パッド)と配線端子とを電気接続部材で電気的に接
続し、前記半導体素子、電気接続部材、及び外部端子
(パッド)と配線端子とが電気的に接続された接続部分
をモールド封止し、前記支持用平板から配線基板を剥離
し、前記剥離された配線基板の裏面に各半導体素子の外
部端子に外部装置接続用端子を形成し、前記各半導体素
子を含む装置をそれぞれの個々に分離する半導体装置の
製造方法である。
Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows. That is, according to the present invention, a wiring board having a large number of wirings for mounting a plurality of elements is attached in advance on a supporting flat plate with an adhesive having a strong adhesive force and easily peeled off, and a predetermined upper surface of the wiring board is attached. A plurality of semiconductor elements (chips) are mounted at positions, and the external terminals (pads) of the semiconductor elements and wiring terminals are electrically connected by an electrical connecting member, and the semiconductor element, the electrical connecting member, and the external terminal ( Pad) and the wiring terminal are electrically connected to each other by molding and sealing, and the wiring board is peeled from the supporting flat plate, and an external device is provided on the back surface of the peeled wiring board to the external terminal of each semiconductor element. It is a method of manufacturing a semiconductor device in which a connection terminal is formed and the device including each semiconductor element is individually separated.

【0006】また、支持用平板の上に、接着力が強くか
つ剥離が容易な接着材で、多数素子搭載用配線があらか
じめ設けられている配線基板を貼り付け、その配線基板
の上面の所定位置に複数個の半導体モジュール(チッ
プ)を搭載し、前記半導体モジュールの外部端子(パッ
ド)と配線端子とを電気接続部材で電気的に接続し、前
記半導体モジュール、電気接続部材、及び外部端子(パ
ッド)と配線端子とが電気的に接続された接続部分をモ
ールド封止し、前記支持用平板から配線基板を剥離し、
前記剥離された配線基板の裏面に各半導体モジュールの
外部端子に外部装置接続用端子を形成し、前記各半導体
モジュール素子を含む装置をそれぞれの個々に分離する
半導体モジュールの製造方法である。また、前記支持用
平板はガラス又は金属材からなり、かつ、前記接着材は
両面接着フィルムからなる。
On the supporting flat plate, a wiring board having a large number of wirings for mounting a plurality of elements is attached in advance with an adhesive having a strong adhesive force and easy to peel off, and a predetermined position on the upper surface of the wiring board is attached. A plurality of semiconductor modules (chips) are mounted on the semiconductor module, and the external terminals (pads) and wiring terminals of the semiconductor module are electrically connected by an electrical connecting member, and the semiconductor module, the electrical connecting member, and the external terminal (pad). ) And the wiring terminals are electrically connected to each other by mold-sealing, and the wiring board is separated from the supporting flat plate,
In the method of manufacturing a semiconductor module, an external device connection terminal is formed on an external terminal of each semiconductor module on the back surface of the peeled wiring board, and the device including each semiconductor module element is individually separated. The supporting flat plate is made of glass or a metal material, and the adhesive is made of a double-sided adhesive film.

【0007】このように、金属やガラス等の支持用平板
上に配線基板(キャリア材)を接着して固定することに
より、前記配線基板(キャリア材)の平担性を向上させ
て組み立てを行うので、組み立てによる不良が低減す
る。これにより半導体装置もしくは半導体モジュールの
信頼が向上する。
As described above, the wiring board (carrier material) is adhered and fixed to the supporting flat plate such as metal or glass, thereby improving the flatness of the wiring board (carrier material) and performing the assembly. Therefore, defects due to assembly are reduced. This improves the reliability of the semiconductor device or the semiconductor module.

【0008】以下、本発明について、図面を参照して実
施の形態(実施例)とともに詳細に説明する。なお、実
施例を説明するための全図において、同一機能を有する
ものは同一符号を付け、その繰り返しの説明は省略す
る。
Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments (embodiments). In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

【0009】[0009]

【発明の実施の形態】(実施例1)図1は、本発明によ
る実施例1のBGA型半導体装置の製造方法の全工程
(プロセス)の概要手順を示すフローチャート、図2〜
図10は図1に示すBGA型半導体装置の製造方法の各
工程を説明するための図である。本実施例1のBGA型
半導体装置の製造方法を図1に沿って説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) FIG. 1 is a flow chart showing an outline procedure of all steps (processes) of a method for manufacturing a BGA type semiconductor device according to a first embodiment of the present invention.
FIG. 10 is a diagram for explaining each step of the manufacturing method of the BGA type semiconductor device shown in FIG. A method of manufacturing the BGA type semiconductor device according to the first embodiment will be described with reference to FIG.

【0010】まず、図2及び図3に示すように、ガラス
又は金属材からなる支持用平板1上に両面接着フィルム
(接着力が強くかつ剥離が容易な接着テープ材)3を載
置し、その上に配線基板(キャリア材)2を載置した
後、それらを熱圧着する(ステップS1)。前記両面接
着フィルム(接着力が強くかつ剥離が容易な接着材)3
としては、例えば、熱硬化性樹脂フィルム、ダイシング
テープ(薄いテープの両面に有機接着剤を塗布したも
の)等を用いる。
First, as shown in FIGS. 2 and 3, a double-sided adhesive film (adhesive tape material having high adhesive strength and easy peeling) 3 is placed on a supporting flat plate 1 made of glass or metal, After the wiring board (carrier material) 2 is placed thereon, they are thermocompression bonded (step S1). Double-sided adhesive film (adhesive with strong adhesive strength and easy peeling) 3
For example, a thermosetting resin film, a dicing tape (thin tape coated with an organic adhesive on both sides), or the like is used.

【0011】前記配線基板2は、例えば、図2及び図3
に示すような多数個取りの1枚の薄い配線基板を用い
る。前記配線基板2は、図2に示すように、半導体チッ
プ搭載用領域2Aがアレイ状に設けられ、それぞれ1個
の領域2Aには半導体装置1個分に対応する配線があら
かじめ設けられている。また、図4及び図5に示すよう
に、支持用平板1上に多数の配線基板2をアレイ状に接
着してもよい。この場合においても、前記配線基板2に
はそれぞれ1個の半導体装置に対応する配線があらかじ
め設けられている。
The wiring board 2 is, for example, as shown in FIGS.
A single thin wiring board is used as shown in FIG. As shown in FIG. 2, the wiring board 2 is provided with semiconductor chip mounting areas 2A in an array, and each area 2A is provided with wiring corresponding to one semiconductor device in advance. Further, as shown in FIGS. 4 and 5, a large number of wiring boards 2 may be bonded in an array on the supporting flat plate 1. Also in this case, the wiring board 2 is provided with wirings corresponding to one semiconductor device in advance.

【0012】次に、図6に示すように、前記配線基板2
の各半導体チップ搭載用領域2A上にペースト(図示し
ていない)により半導体チップ4を接着固定する(ステ
ップS2)。前記半導体チップ4の外部端子(パッド)
と配線端子とを金ボンディングワイヤ5で電気的に接続
する(ステップS3)。前記図4及び図5に示すように
多数の配線基板2を接着した場合は、この各配線基板2
上にペーストにより半導体チップ4を接着する。
Next, as shown in FIG. 6, the wiring board 2
The semiconductor chip 4 is adhered and fixed onto each semiconductor chip mounting area 2A by paste (not shown) (step S2). External terminals (pads) of the semiconductor chip 4
And the wiring terminal are electrically connected with the gold bonding wire 5 (step S3). When a large number of wiring boards 2 are bonded as shown in FIGS. 4 and 5, each wiring board 2
The semiconductor chip 4 is adhered to the top by a paste.

【0013】次に、図7に示すように、前記半導体チッ
プ4、金ボンディングワイヤ5、及び前記接続部分を樹
脂等のレジン6でモールド封止する(ステップS4)。
次に、図8に示すように、前記支持用平板1から両面接
着フィルム(接着力が強くかつ剥離が容易な接着材)3
をはがして配線基板2を剥離する(ステップS5)。こ
の剥離された配線基板2の裏面の各半導体装置に対応す
る位置に、図10(b)に示すように、ランド(図示せ
ず)と金属ボール等からなる外部装置接続用端子7を形
成する(ステップS6)。この状態で配線基板2上の各
半導体素子を含む装置を、図9に示す破線に沿ってダイ
シングし、それぞれ個々の半導体装置に分離する(ステ
ップS7)ことにより、図10(a図は平面図、b図は
側面図)に示すような各半導体装置が得られる。
Next, as shown in FIG. 7, the semiconductor chip 4, the gold bonding wire 5, and the connecting portion are molded and sealed with a resin 6 such as a resin (step S4).
Next, as shown in FIG. 8, a double-sided adhesive film (adhesive having strong adhesive strength and easy peeling) 3 from the supporting flat plate 1 is used.
Then, the wiring board 2 is peeled off (step S5). As shown in FIG. 10B, an external device connecting terminal 7 including a land (not shown) and a metal ball is formed on the back surface of the peeled wiring substrate 2 at a position corresponding to each semiconductor device. (Step S6). In this state, the device including each semiconductor element on the wiring board 2 is diced along the broken line shown in FIG. 9 to separate each into individual semiconductor devices (step S7), and thus FIG. , B are side views), each semiconductor device is obtained.

【0014】以上説明したように、本実施例1によれ
ば、前記配線基板(キャリア材)2の平担性を向上させ
て組み立てを行うので、組み立てによる不良を低減する
ことができる。これにより半導体装置の信頼を向上する
ことができる。
As described above, according to the first embodiment, since the flatness of the wiring board (carrier material) 2 is improved to perform the assembly, defects due to the assembly can be reduced. Thereby, the reliability of the semiconductor device can be improved.

【0015】(実施例2)図11は、本発明の実施例2
のBGA型半導体モジュールの製造方法の工程を説明す
るための平面図であり、図12は図11の側面図であ
る。本実施例2のBGA型半導体装置の製造方法は、図
11及び図12に示すように、前記実施例1の半導体チ
ップの代りに半導体モジュールチップとしたものであ
り、図4及び図5に示すように、支持用平板1上に多数
の半導体モジュールの配線基板(キャリア材)2’をア
レイ状に接着したものである。配線基板2’は配線基板
2を小片化したものである。
(Second Embodiment) FIG. 11 shows a second embodiment of the present invention.
12 is a plan view for explaining a step of the method for manufacturing the BGA type semiconductor module of FIG. 12, and FIG. 12 is a side view of FIG. 11. As shown in FIGS. 11 and 12, in the method of manufacturing the BGA type semiconductor device of the second embodiment, a semiconductor module chip is used instead of the semiconductor chip of the first embodiment, and shown in FIGS. As described above, a large number of wiring boards (carrier materials) 2'of semiconductor modules are adhered in an array on the supporting flat plate 1. The wiring board 2'is a small piece of the wiring board 2.

【0016】本実施例2の製造工程は、前記実施例1と
同様であり、前記実施例1と同様の作用効果を奏する。
すなわち、前記配線基板(キャリア材)2’の平担性を
向上させて組み立てを行うので、組み立てによる不良を
低減することができ、かつ、半導体モジュールの信頼を
向上することができる。
The manufacturing process of the second embodiment is the same as that of the first embodiment and has the same effects as the first embodiment.
That is, since the flatness of the wiring board (carrier material) 2'is improved to perform the assembly, defects due to the assembly can be reduced and the reliability of the semiconductor module can be improved.

【0017】さらに、小片化された配線基板(キャリア
材)2’の良品のみを支持用平板1に接着することによ
り、その後の半導体チップ接着、ワイヤボンディング、
樹脂封止等の組立の工程能力低下を生ずることがなく、
コストアップ防止となる。
Further, by adhering only the non-defective pieces of the wiring board (carrier material) 2'which have been cut into small pieces to the supporting flat plate 1, the subsequent semiconductor chip bonding, wire bonding,
Without lowering the assembly process capability such as resin encapsulation,
Prevents cost increase.

【0018】なお、前記実施例では、BGA型半導体装
置及びBGA型半導体モジュールを例として説明した
が、本発明は、LGA型半導体装置及びLGA型半導体
モジュールに適用できる。LGA型は、前記薄い配線基
板2,2’の外部装置接続用端子がランドからなり、金
属ボールを有しないものである点がBGA型と異なる。
すなわち、BGA型パッケージ用端子と、LGA型パッ
ケージ用端子の違いだけであって、半導体装置及び半導
体モジュールの製造工程はほとんど同じである。
In the above embodiments, the BGA type semiconductor device and the BGA type semiconductor module have been described as examples, but the present invention can be applied to the LGA type semiconductor device and the LGA type semiconductor module. The LGA type is different from the BGA type in that the terminals for external device connection of the thin wiring boards 2 and 2'include lands and do not have metal balls.
That is, the manufacturing steps of the semiconductor device and the semiconductor module are almost the same except for the difference between the BGA type package terminal and the LGA type package terminal.

【0019】以上、本発明を、前記実施例に基づき具体
的に説明したが、本発明は、前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲において種々変
更可能であることは勿論である。
Although the present invention has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

【0020】[0020]

【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、以
下のとおりである。すなわち、本発明によれば、金属や
ガラス等の基板上に配線基板(キャリア材)を接着して
固定することにより、前記配線基板(キャリア材)の平
担性を向上させて組み立てを行うので、組み立てによる
不良を低減することができる。これにより半導体装置も
しくは半導体モジュールの信頼を向上することができ
る。
The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, according to the present invention, the wiring board (carrier material) is adhered and fixed onto a substrate such as metal or glass, so that the flatness of the wiring board (carrier material) is improved and the assembly is performed. It is possible to reduce defects due to assembly. Thereby, the reliability of the semiconductor device or the semiconductor module can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による実施例1のBGA型半導体装置の
製造方法の工程(プロセス)の概要手順を示すフローチ
ャートである。
FIG. 1 is a flowchart showing a schematic procedure of steps of a method for manufacturing a BGA type semiconductor device according to a first embodiment of the present invention.

【図2】本実施例1のBGA型半導体装置の製造方法の
ステップS1の工程を説明するための平面図である。
FIG. 2 is a plan view for explaining the process of step S1 of the method for manufacturing the BGA type semiconductor device of the first embodiment.

【図3】図2の側面図である。FIG. 3 is a side view of FIG.

【図4】本実施例1のBGA型半導体装置の製造方法の
ステップS1の変形例の工程を説明するための平面図で
ある。
FIG. 4 is a plan view for explaining a process of a modified example of step S1 of the method for manufacturing the BGA type semiconductor device of the first embodiment.

【図5】図4の側面図である。FIG. 5 is a side view of FIG.

【図6】本実施例1のBGA型半導体装置の製造方法の
ステップS2、S3の工程を説明するための平面図であ
る。
FIG. 6 is a plan view for explaining steps S2 and S3 of the method for manufacturing the BGA type semiconductor device according to the first embodiment.

【図7】本実施例1のBGA型半導体装置の製造方法の
ステップS4の工程を説明するための平面図である。
FIG. 7 is a plan view for explaining the process of step S4 of the method for manufacturing the BGA type semiconductor device of the first embodiment.

【図8】本実施例1のBGA型半導体装置の製造方法の
ステップS5の工程を説明するための平面図である。
FIG. 8 is a plan view for explaining the process of step S5 of the method for manufacturing the BGA type semiconductor device of the first embodiment.

【図9】本実施例1のBGA型半導体装置の製造方法の
ステップS7の工程を説明するための平面図である。
FIG. 9 is a plan view for explaining the process of step S7 of the method for manufacturing the BGA type semiconductor device of the first embodiment.

【図10】本実施例1のBGA型半導体装置の完成装置
を示す図である。
FIG. 10 is a diagram showing a completed device of the BGA type semiconductor device of the first embodiment.

【図11】本実施例2のBGA型半導体モジュールの製
造方法の工程を説明するための平面図である。
FIG. 11 is a plan view for explaining the steps of the method for manufacturing the BGA type semiconductor module of the second embodiment.

【図12】図11の側面図である。FIG. 12 is a side view of FIG. 11.

【符号の説明】[Explanation of symbols]

1…支持用平板 2、2’…配線
基板(キャリア材) 2A…半導体チップ搭載領域 3…両面接着フ
ィルム 4…半導体チップ 5…金ボンディ
ングワイヤ 6…レジン 7…外部装置接
続用端子
1 ... Supporting flat plate 2, 2 '... Wiring board (carrier material) 2A ... Semiconductor chip mounting area 3 ... Double-sided adhesive film 4 ... Semiconductor chip 5 ... Gold bonding wire 6 ... Resin 7 ... External device connection terminal

フロントページの続き (72)発明者 鈴木 一成 東京都小平市上水本町5丁目22番1号 株 式会社日立超エル・エス・アイ・システム ズ内 (72)発明者 宮木 美典 東京都小平市上水本町五丁目20番1号 株 式会社日立製作所半導体グループ内Continued front page    (72) Inventor Issei Suzuki             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Yoshinori Miyaki             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 支持用平板の上に、接着力が強くかつ剥
離が容易な接着材で、多数素子搭載用配線があらかじめ
設けられている配線基板を貼り付ける工程と、その配線
基板の上面の所定位置に複数個の半導体素子(チップ)
を搭載する工程と、前記半導体素子の外部端子(パッ
ド)と配線端子とを電気接続部材で電気的に接続する工
程と、前記半導体素子、電気接続部材、及び外部端子
(パッド)と配線端子とが電気的に接続された接続部分
をモールド封止する工程と、前記支持用平板から配線基
板を剥離する工程と、前記剥離された配線基板の裏面に
各半導体素子の外部端子に外部装置接続用端子を形成す
る工程と、前記各半導体素子を含む装置をそれぞれの個
々に分離する工程とを具備することを特徴とする半導体
装置製造方法。
1. A step of adhering a wiring board on which a plurality of element mounting wirings are provided in advance on a supporting flat plate with an adhesive material having a strong adhesive force and easy to peel off, and a top surface of the wiring board. Multiple semiconductor devices (chips) at predetermined positions
And a step of electrically connecting an external terminal (pad) and a wiring terminal of the semiconductor element with an electrical connection member, the semiconductor element, the electrical connection member, and an external terminal (pad) and a wiring terminal A step of mold-sealing a connection portion electrically connected to each other, a step of peeling the wiring board from the supporting flat plate, and an external device connection to an external terminal of each semiconductor element on the back surface of the peeled wiring board. A method of manufacturing a semiconductor device, comprising: a step of forming a terminal; and a step of individually separating a device including each of the semiconductor elements.
【請求項2】 支持用平板の上に、接着力が強くかつ剥
離が容易な接着材で、多数素子搭載用配線があらかじめ
設けられている配線基板を貼り付ける工程と、その配線
基板の上面の所定位置に複数個の半導体モジュール(チ
ップ)を搭載する工程と、前記半導体モジュールの外部
端子(パッド)と配線端子とを電気接続部材で電気的に
接続する工程と、前記半導体モジュール、電気接続部
材、及び外部端子(パッド)と配線端子とが電気的に接
続された接続部分をモールド封止する工程と、前記支持
用平板から配線基板を剥離する工程と、前記剥離された
配線基板の裏面に各半導体モジュールの外部端子に外部
装置接続用端子を形成する工程と、前記各半導体モジュ
ール素子を含む装置をそれぞれの個々に分離する工程と
を具備することを特徴とする半導体モジュールの製造方
法。
2. A step of adhering a wiring board, on which a multi-element mounting wiring is preliminarily provided, on a supporting flat plate with an adhesive material having a strong adhesive force and easy to peel off, and a step of attaching an upper surface of the wiring board. A step of mounting a plurality of semiconductor modules (chips) at predetermined positions; a step of electrically connecting an external terminal (pad) and a wiring terminal of the semiconductor module with an electrical connecting member; the semiconductor module, an electrical connecting member , And a step of mold-sealing the connection portion where the external terminal (pad) and the wiring terminal are electrically connected, a step of peeling the wiring board from the supporting flat plate, and a step of removing the wiring board on the back surface of the peeled wiring board. The method further comprises a step of forming an external device connection terminal on an external terminal of each semiconductor module, and a step of individually separating the device including each semiconductor module element. And a method for manufacturing a semiconductor module.
【請求項3】 前記支持用平板はガラス又は金属材から
なり、かつ、前記接着材は両面接着フィルムからなるこ
とを特徴とする請求項1に記載の半導体装置製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the supporting flat plate is made of glass or a metal material, and the adhesive is made of a double-sided adhesive film.
JP2001193042A 2001-06-26 2001-06-26 Manufacturing method of semiconductor device Expired - Fee Related JP4656766B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001193042A JP4656766B2 (en) 2001-06-26 2001-06-26 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001193042A JP4656766B2 (en) 2001-06-26 2001-06-26 Manufacturing method of semiconductor device

Publications (3)

Publication Number Publication Date
JP2003007913A true JP2003007913A (en) 2003-01-10
JP2003007913A5 JP2003007913A5 (en) 2008-08-07
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Family

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP4656766B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101847103B1 (en) 2012-04-02 2018-04-10 후지 덴키 가부시키가이샤 Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08107161A (en) * 1994-06-22 1996-04-23 Seiko Epson Corp Electronic part, electronic part material, and manufacture of electronic part
JPH10284525A (en) * 1997-04-03 1998-10-23 Shinko Electric Ind Co Ltd Method for producing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08107161A (en) * 1994-06-22 1996-04-23 Seiko Epson Corp Electronic part, electronic part material, and manufacture of electronic part
JPH10284525A (en) * 1997-04-03 1998-10-23 Shinko Electric Ind Co Ltd Method for producing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101847103B1 (en) 2012-04-02 2018-04-10 후지 덴키 가부시키가이샤 Semiconductor device

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