KR100468233B1 - Power semiconductor die attach process using conductive adhesive film - Google Patents

Power semiconductor die attach process using conductive adhesive film Download PDF

Info

Publication number
KR100468233B1
KR100468233B1 KR10-2002-7006634A KR20027006634A KR100468233B1 KR 100468233 B1 KR100468233 B1 KR 100468233B1 KR 20027006634 A KR20027006634 A KR 20027006634A KR 100468233 B1 KR100468233 B1 KR 100468233B1
Authority
KR
South Korea
Prior art keywords
die
film
substrate
area
adhesive film
Prior art date
Application number
KR10-2002-7006634A
Other languages
Korean (ko)
Other versions
KR20020059782A (en
Inventor
파비에르마크
Original Assignee
인터내쇼널 렉티파이어 코포레이션
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 인터내쇼널 렉티파이어 코포레이션 filed Critical 인터내쇼널 렉티파이어 코포레이션
Publication of KR20020059782A publication Critical patent/KR20020059782A/en
Application granted granted Critical
Publication of KR100468233B1 publication Critical patent/KR100468233B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

많은 수의 동일한 구조들을 갖는 반도체 웨이퍼(21)에 큰 면적의 접착 필름(20)을 부착한다. 이후, 필름(20) 및 웨이퍼(21)를 동시에 단일화한 다음, 필름이 부착되어 있는 각 다이를 리드 프레임 상에 배치한다. 상기 필름을 완전히 경화시켜 반도체 다이를 리드 프레임에 부착한다. 공통 기판 상에 복수의 다이들을 다이 옆에 다이가 있는 형태로 장착하거나, 1개의 다이를 기판(11) 상에 있는 제 2 다이 상에 장착할 수 있다.A large area of the adhesive film 20 is attached to the semiconductor wafer 21 having a large number of identical structures. Thereafter, the film 20 and the wafer 21 are simultaneously unified, and then, each die to which the film is attached is placed on the lead frame. The film is fully cured to attach the semiconductor die to the lead frame. A plurality of dies may be mounted on a common substrate in the form of a die next to the die, or one die may be mounted on a second die on the substrate 11.

Description

도전성 접착 필름을 이용한 파워 반도체 다이 부착 방법{POWER SEMICONDUCTOR DIE ATTACH PROCESS USING CONDUCTIVE ADHESIVE FILM}Power semiconductor die attach method using conductive adhesive film {POWER SEMICONDUCTOR DIE ATTACH PROCESS USING CONDUCTIVE ADHESIVE FILM}

다이오드, MOSFET, IGBT 등과 같은 파워 반도체 다이는 통상적으로 에폭시 수지, 열가소성 물질, 솔더 등과 같은 전기적으로 도전성인 물질들에 의해, 또는 전기적인 절연이 요구되는 경우에는 전기적으로 절연성인 물질들에 의해, 도전성 리드 프레임들 또는 다른 기판들에 부착된다. 이러한 방법은 웨이퍼로부터 다이를 단일화(singulation)한 후에 개별적인 다이에 대해 연속적으로 수행되기 때문에 시간이 걸린다.Power semiconductor dies, such as diodes, MOSFETs, IGBTs, etc., are typically conductive by electrically conductive materials such as epoxy resins, thermoplastics, solders, or by electrically insulating materials where electrical insulation is required. It is attached to lead frames or other substrates. This method is time consuming because it is performed continuously on individual dies after singulation of the dies from the wafer.

본 발명은 반도체 디바이스들에 관한 것으로서, 특히 열적으로 그리고/또는 전기적으로 도전성인 기판에 파워 반도체 다이(power semiconductor die)를 부착하는 새로운 방법에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor devices, and more particularly to a new method of attaching a power semiconductor die to a thermally and / or electrically conductive substrate.

도 1 및 2는 각각 종래 기술의 다이 부착의 평면도 및 측면도이다.1 and 2 are plan and side views, respectively, of prior art die attach.

도 3 및 4는 각각 도전성 접착 필름에 의해 기판에 부착된 파워 반도체 다이의 평면도 및 측면도이다.3 and 4 are plan and side views, respectively, of a power semiconductor die attached to a substrate by a conductive adhesive film.

도 5는 단일화 이전의 큰 면적의 접착 필름 및 반도체 디바이스의 투시도이다.5 is a perspective view of a large area adhesive film and semiconductor device prior to unification.

도 6는 접착된 후의 도 5의 투시도이다.6 is a perspective view of FIG. 5 after being bonded.

도 7은 기판에 부착되기 전의, 도 6의 어셈블리로부터 단일화된 하나의 다이/필름 스택을 도시한다.FIG. 7 shows one die / film stack unified from the assembly of FIG. 6 before being attached to the substrate. FIG.

도 8은 열 경화 및 본딩 후의 도 8의 어셈블리를 도시한다.8 shows the assembly of FIG. 8 after thermal curing and bonding.

도 9는 다이 위에 다이가 있는 어셈블리(die-on-die assembly)로서 적용되는 본 발명의 방법을 도시한다.9 illustrates the method of the present invention applied as a die-on-die assembly on a die.

도 10은 공통 기판 상에서 다이 옆에 다이가 있는 어셈블리(side-by-side assembly)로서 적용되는 본 발명의 방법을 도시한다.FIG. 10 illustrates the method of the present invention applied as a side-by-side assembly on a common substrate next to the die.

본 발명에 따르면, 전기적으로 도전성이거나 절연성인 접착 필름(adhesive film)들을 파워 반도체들을 위한 다이 부착 물질로서 이용한다. 또한, 이러한 접착 필름들을 다이 단일화 단계 이전에 파워 반도체 웨이퍼들에 부착한다.According to the present invention, electrically conductive or insulating adhesive films are used as die attach material for power semiconductors. In addition, these adhesive films are attached to the power semiconductor wafers prior to the die singulation step.

그런 다음, 이러한 접착 필름들을 이용하여 저 파워 집적 회로들을 리드 프레임들에 본딩시킨다. 본 발명에 따르면, 도전성 또는 절연성 접착 필름들을 이용하여 파워 반도체들을 기판들/리드 프레임들에 본딩시킨다.These adhesive films are then used to bond the low power integrated circuits to the lead frames. According to the present invention, power semiconductors are bonded to substrates / lead frames using conductive or insulating adhesive films.

종래에는, 접착 필름들을 미리 자른 다음, 필름 상에 다이를 배치하기 전에 기판 상에 배치한다. 이후, 이렇게 얻어진 기판/필름/다이 어셈블리를 부분적으로 열처리하여 다이/리드 프레임 간에 접착이 이루어지게 한다. 본 발명에 따르면, 다이 단일화 단계 이전에 접착 필름을 파워 반도체 웨이퍼 상에 배치한다. 이후, 웨이퍼/접착 필름 스택을 종래의 단일화 방법들을 이용하여 분리함으로써, 접착 필름이 미리 부착된 다이를 생성한다. 이후, 분리된 다이/필름 스택을 기판/리드 프레임 상에 배치한 다음, 열처리에 의해 접착 필름을 재활성화시켜 본딩을 촉진시키고 경화를 완료한다.Conventionally, the adhesive films are cut in advance and then placed on a substrate before placing the die on the film. Subsequently, the substrate / film / die assembly thus obtained is partially heat treated to bond between the die / lead frames. According to the present invention, the adhesive film is placed on a power semiconductor wafer prior to the die singulation step. Thereafter, the wafer / adhesive film stack is separated using conventional unification methods to produce a die with the adhesive film pre-attached. Thereafter, the separated die / film stack is placed on the substrate / lead frame, and then heat treated to reactivate the adhesive film to promote bonding and complete curing.

본 발명은 많은 장점들을 제공한다. 즉, 종래의 파워 반도체 다이 부착은 페이스트 또는 액체 형태의 에폭시 수지 또는 솔더 타입의 접착제들을 이용한다. 이러한 물질들은 종종 다이 본딩을 하는 동안 다이의 에지로부터 기판/리드 프레임 상으로 흘러 넘친다. 이렇게 물질들이 흘러 넘치게 되면, 리드 프레임/기판 상에 배치할 수 있는 다이의 사이즈를 제한한다. 접착 필름을 이용하여 이러한 넘쳐 흐름을 제거한다. 이렇게 되면, 소정 사이즈의 패키지에 보다 큰 다이를 배치할 수 있게 된다. 본딩 라인의 두께 또한 접착 필름의 두께에 의해 설정되어 일정하게 된다. 본딩 내의 공극들이 또한 존재하지 않게 된다.The present invention provides many advantages. That is, conventional power semiconductor die attach uses epoxy resin or solder type adhesives in paste or liquid form. These materials often flow from the edge of the die onto the substrate / lead frame during die bonding. This overflowing material limits the size of the die that can be placed on the lead frame / substrate. An adhesive film is used to remove this overflow. This makes it possible to place a larger die in a package of a predetermined size. The thickness of the bonding line is also set and made constant by the thickness of the adhesive film. The voids in the bond also become absent.

또한, 다이 단일화 이전에 전기적으로 도전성이거나 (또는 전기적으로 절연성인) 접착 필름을 파워 반도체 웨이퍼 상에 미리 본딩하게 되면, 어셈블리 동안 별도의 픽 앤 플레이스(pick and place) 단계가 불필요해진다. 이에 따라, 제조 장비의 비용이 감소되어 사이클 타임(cycle time)이 짧아진다.In addition, the pre-bonding of an electrically conductive (or electrically insulating) adhesive film onto the power semiconductor wafer prior to die singulation eliminates the need for a separate pick and place step during assembly. This reduces the cost of manufacturing equipment and shortens the cycle time.

도 1 및 2는 파워 반도체 다이(10) 및 도전성 기판(11)을 도시하는바, 이들은 솔더 또는 에폭시 수지 부착 물질(12)에 의해 부착된다. 주목할 사항으로서, 상기 물질(12)은 통상적으로 흘러 넘치기 때문에, 소정 면적의 기판 상에서의 다이의 최대 사이즈를 한정한다.1 and 2 show a power semiconductor die 10 and a conductive substrate 11, which are attached by solder or epoxy resin attachment substance 12. Note that the material 12 typically overflows, thus limiting the maximum size of the die on a substrate of a given area.

도 3 및 4는, 얇고 유연한 접착 필름(13)을 이용하여 다이(10)와 기판(11)을 본딩하는 도 1 및 2의 다이(10)를 도시한다. 필름(13)은 전기적으로 도전성이거나 절연성이며, 열 경화가 가능하다. 도 3 및 4에서 볼 수 있는 바와 같이, 이러한 필름을 이용하게 되면 넘쳐 흐름을 없애기 때문에, 도 1 및 2의 기판과 같은 면적의 기판(11) 상에 보다 큰 면적의 다이(10)를 가능하게 한다.3 and 4 show the die 10 of FIGS. 1 and 2 bonding the die 10 and the substrate 11 using a thin flexible adhesive film 13. The film 13 is electrically conductive or insulating and can be thermally cured. As can be seen in Figures 3 and 4, the use of such a film eliminates the overflow, thereby allowing a larger area die 10 on a substrate 11 of the same area as the substrates of Figures 1 and 2. do.

도 5 내지 8은 본 발명의 새로운 방법을 도시한다. 도 5는 통상적인 방법으로 동시에 처리되는 많은 수의 동일한 파워 반도체 다이를 포함하는 반도체 디바이스 웨이퍼(21)를 도시한다. 따라서, 웨이퍼는 수 백개의 동일한 수직 전도 파워 MOSFET 다이를 포함할 수 있는바, 이들의 상부 표면에는 통상적으로 도전성 소스 전극 및 하부의 도전성 드레인 전극으로 덮여져 있는 P/N 접합들을 있다. 통상적인 분리 장치(sawing apparatus)를 이용하여 웨이퍼를 분리함으로써, 웨이퍼의 다이를 단일화한다. 이후, 다이의 드레인 전극을 기판에 솔더링 또는 에폭시 수지 본딩함으로써, 개별적인 다이를 리드 프레임 또는 다른 기판 상에 장착한다.5-8 illustrate a novel method of the present invention. 5 shows a semiconductor device wafer 21 comprising a large number of identical power semiconductor dies processed simultaneously in a conventional manner. Thus, a wafer may include hundreds of identical vertical conducting power MOSFET dies, on their upper surface having P / N junctions that are typically covered by a conductive source electrode and a conductive drain electrode below. The die of the wafer is unified by isolating the wafer using a conventional sawing apparatus. The individual dies are then mounted on a lead frame or other substrate by soldering or epoxy resin bonding the drain electrodes of the die to the substrate.

본 발명에 따르면, 전형적으로 약 6 인치의 직경을 가질 수 있는 웨이퍼의 사이즈로 접착 필름(20)을 절단한다.According to the present invention, the adhesive film 20 is cut to the size of a wafer, which may typically have a diameter of about 6 inches.

필름(20)은 바람직하게는 "캡톤(KAPTON)" 필름으로서 공지된 폴리이미드 필름인바, 이는 전기적인 권선 절연(electrical winding insulation) 등을 위해 PC 보드들, "플렉서블(flexible)" 회로에서 빈번하게 이용된다. 이 캡톤 폴리이미드는 우수한 절연체이다. 이후, 웨이퍼(21) 및 필름(20)을 서로 적층한 다음 예열하여 접착을 향상시키지만, 필름(20)을 완전히 경화시키지는 않는다.The film 20 is preferably a polyimide film known as a "KAPTON" film, which is frequently used in PC boards, "flexible" circuits for electrical winding insulation and the like. Is used. This Kapton polyimide is an excellent insulator. Thereafter, the wafers 21 and the film 20 are laminated to each other and then preheated to improve adhesion, but do not completely cure the film 20.

이후, 도 6에 개략적으로 도시한 바와 같이, 필름(20) 및 웨이퍼(21)를 절단 라인들(22)을 따라 동시에 분리하여 개별적인 다이를 형성한다. 통상적인 프레임 또는 지지체가 상기 분리된 필름/다이 스택들을 적소에 유지한 다음, 스택들을 통상적인 픽 앤 플레이스 장치(pick and place apparatus)에 배치하게 되면, 단일화된 디바이스들은 자동 방식으로 각각의 가열된 리드 프레임들 또는 기판들 상의 장착될 위치로 픽업되어 옮겨진다.6, the film 20 and the wafer 21 are then simultaneously separated along the cutting lines 22 to form individual dies. If a conventional frame or support holds the separated film / die stacks in place and then places the stacks in a conventional pick and place apparatus, the unitized devices are automatically Picked up and moved to the position to be mounted on the lead frames or substrates.

따라서, 도 7에 도시한 바와 같이, 통상적인 픽 앤 플레이스 장치를 이용하여 다이/필름 스택(21/20)을 각 기판(11) 상에 배치한다. 바람직하게는, 압력을 가하여, 예열된 기판(11)의 표면에 스택(21/20)을 누른다.Therefore, as shown in FIG. 7, the die / film stack 21/20 is disposed on each substrate 11 using a conventional pick and place apparatus. Preferably, pressure is applied to the stack 21/20 against the surface of the preheated substrate 11.

이후, 다이/필름 스택(21/20) 및 기판(11)을 약 260℃로 가열하여 필름(21)을 완전히 경화시킴으로써, 기판(11)에 대한 본딩을 형성한다.The die / film stack 21/20 and the substrate 11 are then heated to about 260 ° C. to completely cure the film 21 to form a bond to the substrate 11.

도 7 및 8의 구조를 실시하여, 다이 위에 다이가 있는 패키지(도 9) 또는 다이 옆에 다이가 있는 패키지(도 10)를 형성할 수 있다. 따라서, 도 9에서는, 접착층들(20) 및 반도체 다이들(21)을 갖는 2개의 동일한 다이들(30 및 31)가 장착하는바, 다이(30) 위에 다이(31)를 장착한다. 다이들(30 및 31)는 각각 다른 종류의 디바이스들, 예를 들어 MOSFET 및 쇼트키 다이오드가 될 수 있으며, 서로 다른 사이즈들 또는 면적들을 가질 수 있다. 대안적으로, 다이(31)는 집적 회로가 될 수 있다.The structures of FIGS. 7 and 8 can be implemented to form a package with a die (FIG. 9) over a die or a package with a die next to the die (FIG. 10). Thus, in FIG. 9, two identical dies 30 and 31 with adhesive layers 20 and semiconductor dies 21 are mounted, which mounts the die 31 over the die 30. Dies 30 and 31 may each be different kinds of devices, for example MOSFETs and Schottky diodes, and may have different sizes or areas. Alternatively, die 31 may be an integrated circuit.

또한, 도 9의 층들(20)은 다이들(30 및 31)을 배면(back to back) 결합할 수있는 적절한 도전성 접착 필름이 될 수 있다.In addition, the layers 20 of FIG. 9 may be any suitable conductive adhesive film capable of backing back the dies 30 and 31.

도 10에 도시한 바와 같이, 다이들(30 및 31)은 각각 MOSFET 및 IC(다이 21)를 포함할 수 있다.As shown in FIG. 10, dies 30 and 31 may include a MOSFET and an IC (die 21), respectively.

필름(20)으로 이용할 수 있는 다른 필름으로는, 알파 금속 383G(RHS) 및 UH2W-E 폴리이미드 필름(LHS)과 같은 열가소성 접착제 페이스트가 있다.Other films that can be used as the film 20 include thermoplastic adhesive pastes such as alpha metal 383G (RHS) and UH2W-E polyimide film (LHS).

지금까지 본 발명을 특정한 실시예들에 관련하여 설명했지만, 다른 많은 변형, 수정 및 다른 용도가 당업자들에게 명백해질 것이다. 따라서, 본 발명은 본원에 개시된 내용에 한정되지 않으며, 첨부된 청구항들에 의해서만 한정되는 것이 바람직하다.While the present invention has been described with reference to specific embodiments, many other variations, modifications, and other uses will become apparent to those skilled in the art. Accordingly, the invention is not limited to the disclosure herein but is preferably limited only by the appended claims.

Claims (11)

기판에 반도체 다이를 결합시키는 방법으로서,As a method of bonding a semiconductor die to a substrate, 제 1 면적을 갖는 얇은 유연성의 열 경화가능한 폴리이미드의 절연성 필름을 제공하는 단계와;Providing an insulating film of thin flexible heat curable polyimide having a first area; 상기 필름을 제 2 면적을 갖는 반도체 웨이퍼 상에 배치하는 단계와, 여기서 상기 반도체 웨이퍼는 복수의 이격된 반도체 다이들을 갖고, 상기 각 반도체 다이는 상기 제 1 면적 보다 작은 제 3 면적을 가지며;Disposing the film on a semiconductor wafer having a second area, wherein the semiconductor wafer has a plurality of spaced apart semiconductor dies, each semiconductor die having a third area less than the first area; 어떠한 외부 압력도 가하지 않으면서 상기 반도체 웨이퍼와 상기 필름을 예열하여 상기 필름을 부분적으로 경화시킴으로써, 상기 필름과 상기 반도체 웨이퍼 간의 접착을 형성하는 단계와;Preheating the semiconductor wafer and the film without applying any external pressure to partially cure the film, thereby forming an adhesion between the film and the semiconductor wafer; 상기 필름과 상기 복수의 동일한 반도체 다이들을 동시에 단일화하여 개별적인 요소들을 형성하는 단계와;Simultaneously unifying the film and the plurality of identical semiconductor dies to form individual elements; 상기 기판을 가열하는 단계와;Heating the substrate; 상기 기판의 상부 표면에 상기 단일화된 다이를 대고, 상기 다이 상의 필름을 상기 기판의 상부 표면에 가압하여 부착하는 단계와; 그리고Placing the unified die on an upper surface of the substrate and pressing and attaching a film on the die to an upper surface of the substrate; And 상기 다이를 상기 기판에 단단히 부착시키기 위해 상기 필름을 완전히 경화시키는 단계를 포함하는 것을 특징으로 하는 방법.Completely curing the film to securely attach the die to the substrate. 제 1 항에 있어서,The method of claim 1, 상기 기판은 전도체 리드 프레임인 것을 특징으로 하는 방법.And the substrate is a conductor lead frame. 삭제delete 삭제delete 제 1 항에 있어서,The method of claim 1, 상기 다이 상의 상기 필름은 상기 기판 상에 어셈블리된 후 상기 다이의 면적과 같은 면적을 갖는 것을 특징으로 하는 방법.And said film on said die has an area equal to that of said die after being assembled on said substrate. 제 1 항에 있어서,The method of claim 1, 제 1 다이로부터 횡방향으로 이동한 위치에서, 위에 제 2 접착 필름을 갖는 제 2 반도체 다이를 상기 기판에 부착하는 단계를 더 포함하는 것을 특징으로 하는 방법.Attaching to the substrate a second semiconductor die having a second adhesive film thereon, at a position laterally moved from the first die. 제 1 항에 있어서,The method of claim 1, 제 2 접착 필름을 갖는 제 2 다이를, 상기 기판에 고정된 다이의 상부에 부착하는 단계를 더 포함하는 것을 특징으로 하는 방법.And attaching a second die having a second adhesive film on top of the die fixed to the substrate. 제 1 항에 있어서,The method of claim 1, 상기 제 1 면적과 상기 제 2 면적은 같은 것을 특징으로 하는 방법.And wherein the first area and the second area are the same. 제 1 항에 있어서,The method of claim 1, 픽 앤 플레이스 장치를 이용하여 상기 다이 및 상기 필름을 상기 기판으로 이동시키는 것을 특징으로 하는 방법.Moving said die and said film to said substrate using a pick and place device. 제 1 항에 있어서,The method of claim 1, 상기 접착 필름은 상기 다이의 상부 표면 보다 작은 면적을 갖는 것을 특징으로 하는 방법.And the adhesive film has an area smaller than the top surface of the die. 제 7 항에 있어서,The method of claim 7, wherein 상기 접착 필름은 상기 다이의 상부 표면 보다 작은 면적을 가지며, 상기 제 2 다이 및 상기 제 2 접착 필름은 모두 상기 접착 필름과 동일한 면적을 갖는 것을 특징으로 하는 방법.Wherein said adhesive film has an area smaller than an upper surface of said die, and wherein said second die and said second adhesive film both have the same area as said adhesive film.
KR10-2002-7006634A 1999-11-24 2000-11-22 Power semiconductor die attach process using conductive adhesive film KR100468233B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16745699P 1999-11-24 1999-11-24
US60/167,456 1999-11-24

Publications (2)

Publication Number Publication Date
KR20020059782A KR20020059782A (en) 2002-07-13
KR100468233B1 true KR100468233B1 (en) 2005-01-26

Family

ID=22607438

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-2002-7006634A KR100468233B1 (en) 1999-11-24 2000-11-22 Power semiconductor die attach process using conductive adhesive film

Country Status (6)

Country Link
JP (1) JP3771843B2 (en)
KR (1) KR100468233B1 (en)
CN (1) CN1187804C (en)
AU (1) AU1927501A (en)
TW (1) TW501207B (en)
WO (1) WO2001039266A1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620651B2 (en) 2001-10-23 2003-09-16 National Starch And Chemical Investment Holding Corporation Adhesive wafers for die attach application
US6781352B2 (en) 2002-12-16 2004-08-24 International Rectifer Corporation One cycle control continuous conduction mode PFC boost converter integrated circuit with integrated power switch and boost converter
WO2005057644A1 (en) * 2003-12-15 2005-06-23 The Furukawa Electric Co., Ltd. Wafer processing tape and method of producing the same
JP2006114649A (en) * 2004-10-14 2006-04-27 Fuji Electric Device Technology Co Ltd Method and apparatus for manufacturing semiconductor device
CN101807531A (en) * 2010-03-30 2010-08-18 上海凯虹电子有限公司 Ultra-thin chip packaging method and packaged body

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2994510B2 (en) * 1992-02-10 1999-12-27 ローム株式会社 Semiconductor device and manufacturing method thereof
US5286679A (en) * 1993-03-18 1994-02-15 Micron Technology, Inc. Method for attaching a semiconductor die to a leadframe using a patterned adhesive layer
JP3467611B2 (en) * 1995-09-29 2003-11-17 日本テキサス・インスツルメンツ株式会社 Method for manufacturing semiconductor device
US5776799A (en) * 1996-11-08 1998-07-07 Samsung Electronics Co., Ltd. Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same

Also Published As

Publication number Publication date
JP3771843B2 (en) 2006-04-26
TW501207B (en) 2002-09-01
CN1187804C (en) 2005-02-02
CN1399794A (en) 2003-02-26
KR20020059782A (en) 2002-07-13
AU1927501A (en) 2001-06-04
WO2001039266A9 (en) 2002-04-18
JP2003515929A (en) 2003-05-07
WO2001039266A1 (en) 2001-05-31

Similar Documents

Publication Publication Date Title
KR100317648B1 (en) Semiconductor device having die adhesively bonded by electrically insulating tape, method and apparatus for die bonding
US5221642A (en) Lead-on-chip integrated circuit fabrication method
US7838340B2 (en) Pre-molded clip structure
CN1303660C (en) Adhesive wafers for die attach application
US9673170B2 (en) Batch process for connecting chips to a carrier
US11830856B2 (en) Semiconductor package and related methods
CN100380653C (en) Semiconductor device and method of manufacturing semiconductor device
US9299592B2 (en) Package structure and packaging method of wafer level chip scale package
KR100468233B1 (en) Power semiconductor die attach process using conductive adhesive film
US6723620B1 (en) Power semiconductor die attach process using conductive adhesive film
CN112005338A (en) Method for simultaneously fabricating multiple wafers on a large carrier with warpage control enhancements
KR20170069924A (en) Semiconductor package and manufacturing method thereof
US10319659B2 (en) Semiconductor package and related methods
US20240112956A1 (en) Wafer composite, semiconductor device and methods of manufacturing a semiconductor circuit
US11222878B2 (en) Electronic power module
KR20000007325A (en) Semiconductor package having chip-on-chip structure and fabricating method of the same
JPH04119644A (en) Mounting of semicondctor element
JP2004153004A (en) Hybrid integrated circuit device and method for manufacturing the same
JP2001210610A (en) Method of manufacturing semiconductor wafer with anisotropic conductive film
JPS59221369A (en) Method for bonding semiconductor chip
JP2002353250A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20130108

Year of fee payment: 9

FPAY Annual fee payment

Payment date: 20140107

Year of fee payment: 10

FPAY Annual fee payment

Payment date: 20150106

Year of fee payment: 11

FPAY Annual fee payment

Payment date: 20160108

Year of fee payment: 12

FPAY Annual fee payment

Payment date: 20170106

Year of fee payment: 13

FPAY Annual fee payment

Payment date: 20180105

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee