JP2003515929A - Power semiconductor die bonding method using conductive adhesive film - Google Patents

Power semiconductor die bonding method using conductive adhesive film

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Publication number
JP2003515929A
JP2003515929A JP2001540836A JP2001540836A JP2003515929A JP 2003515929 A JP2003515929 A JP 2003515929A JP 2001540836 A JP2001540836 A JP 2001540836A JP 2001540836 A JP2001540836 A JP 2001540836A JP 2003515929 A JP2003515929 A JP 2003515929A
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Japan
Prior art keywords
semiconductor die
substrate
die
adhesive film
area
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Granted
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JP2001540836A
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Japanese (ja)
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JP3771843B2 (en
Inventor
パビエール マーク
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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Publication of JP3771843B2 publication Critical patent/JP3771843B2/en
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Abstract

(57)【要約】 大面積の接着フィルム（２０）を、多数の同一の構造を含む半導体ウェーハ（２１）に付着させる。次に、接着フィルム（２０）およびウェーハ（２１）を同時にシンギュレーションし、接着フィルムをその上に有する個々の半導体ダイを、リードフレーム上に配置し、接着フィルムを完全に硬化させて、半導体ダイをリードフレームに接着させる。複数の半導体ダイを、共通の基板（１１）上に横に並べて装着することができ、または１つの半導体ダイを、基板（１１）上にある第２の半導体ダイ上に装着することができる。 (57) Summary An adhesive film (20) having a large area is attached to a number of semiconductor wafers (21) including the same structure. Next, the adhesive film (20) and the wafer (21) are simultaneously singulated, individual semiconductor dies having the adhesive film thereon are placed on a lead frame, and the adhesive film is completely cured to produce a semiconductor. Glue the die to the lead frame. Multiple semiconductor dies can be mounted side by side on a common substrate (11), or one semiconductor die can be mounted on a second semiconductor die on the substrate (11).

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】 （発明の背景） 本発明は、半導体デバイスに関するものであり、より詳しくは、伝熱性および
／または導電性の基板にパワー半導体ダイ（ｐｏｗｅｒ ｓｅｍｉｃｏｎｄｕｃ
ｔｏｒ ｄｉｅ）を接着させるための新規な方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a power semiconductor die on a thermally conductive and / or electrically conductive substrate.
to a new method for adhering tor dies).

【０００２】 ダイオード、ＭＯＳＦＥＴ、ＩＧＢＴなどのパワー半導体ダイは、通常は、エ
ポキシ樹脂、熱可塑性樹脂、半田などの導電性材料によって、または電気的分離
が所望ならば、電気絶縁性材料によって、導電性のリードフレームまたは他の基
板に付着される。この方法は、ウェーハからダイをシンギュレーション（ｓｉｎ
ｇｕｌａｔｉｏｎ）した後に、個々のダイに関して順々に行われるので時間が掛
かる。Power semiconductor dies, such as diodes, MOSFETs, IGBTs, are typically made electrically conductive by electrically conductive materials such as epoxy resins, thermoplastics, solders or, if electrical isolation is desired, by electrically insulating materials. Attached to a lead frame or other substrate. This method singulates the die from the wafer.
After gluing, it is time consuming as it is done sequentially for each die.

【０００３】 （発明の簡単な説明） 本発明によれば、導電性または電気絶縁性であることができる接着フィルムを
、パワー半導体のためのダイ付着材料として用いる。更に、そのような接着フィ
ルムは、ダイシンギュレーション段階前に、パワー半導体ウェーハに付着させる
。Brief Description of the Invention According to the present invention, an adhesive film, which can be electrically conductive or electrically insulating, is used as a die attach material for power semiconductors. Further, such an adhesive film is applied to the power semiconductor wafer before the die singulation step.

【０００４】 次に、接着フィルムを用いて、低電力集積回路をリードフレームにボンディン
グする。本発明によれば、導電性または電気絶縁性の接着フィルムを用いて、パ
ワー半導体を、基板／リードフレームにボンディングする。Next, an adhesive film is used to bond the low power integrated circuit to the lead frame. According to the present invention, a power semiconductor is bonded to a substrate / lead frame using a conductive or electrically insulating adhesive film.

【０００５】 従来技術における接着フィルムは、プレカットされ、フィルム上にダイを配置
する前に基板上に配置される。次に、得られた基板／フィルム／ダイアセンブリ
は、ダイ／リードフレーム間の接着を向上させるために部分的に熱処理される。
本発明によれば、接着フィルムは、ダイシンギュレーション段階前に、パワー半
導体ウェーハ上に配置する。次に、ウェーハ／接着フィルムのスタックを、従来
のシンギュレーション法を用いて切り分けて、接着フィルムを予め付着したダイ
を製作する。次に、熱処理により接着剤を再活性化させて、ボンディングを促進
し、硬化を完了させる前に、切り分けたダイ／フィルムのスタックを基板／リー
ドフレーム上に配置する。The adhesive film in the prior art is pre-cut and placed on the substrate before placing the die on the film. The resulting substrate / film / die assembly is then partially heat treated to improve the die / leadframe adhesion.
According to the invention, the adhesive film is placed on the power semiconductor wafer before the die singulation step. The wafer / adhesive film stack is then cut using a conventional singulation method to produce a die with the adhesive film pre-attached. The heat-treated adhesive then reactivates the adhesive to place the cut die / film stack on the substrate / leadframe before promoting bonding and completing the cure.

【０００６】 いくつかの利点が本発明によって提供される。すなわち、従来のパワー半導体
ダイの付着では、エポキシ樹脂タイプまたは半田タイプの接着剤をペーストまた
は液体の形態で使用する。これらの材料は、しばしば、ダイボンディング中に、
ダイの縁から基板／リードフレーム上にこぼれる。このこぼれにより、リードフ
レーム／基板上に配置できるダイのサイズが限定される。接着フィルムを用いる
ことによって、そのようなこぼれがなくなる。その結果、所与のサイズのパッケ
ージ中により大きなダイを配置することができる。ボンド線（ｂｏｎｄ ｌｉｎ
ｅ）の厚さも、接着フィルムの厚さによって設定され、一定となる。接着剤層中
にはボイドも存在しなくなる。Several advantages are provided by the present invention. That is, in the conventional attachment of a power semiconductor die, an epoxy resin type or solder type adhesive is used in the form of paste or liquid. These materials are often used during die bonding
Spill from die edge onto substrate / leadframe. This spill limits the size of the die that can be placed on the leadframe / substrate. By using an adhesive film, such spills are eliminated. As a result, a larger die can be placed in a given size package. Bond line
The thickness of e) is also set by the thickness of the adhesive film and becomes constant. There are no voids in the adhesive layer.

【０００７】 ダイシンギュレーション前に、導電性または（電気絶縁性）接着フィルムを、
パワー半導体ウェーハ上に予めボンディングすると、組立て中の余計なピックア
ンドプレイス段階も不要となる。したがって、製造装置のコストが下がり、サイ
クル時間が短くなる。Prior to die singulation, a conductive or (electrically insulating) adhesive film was
Pre-bonding on the power semiconductor wafer also eliminates the extra pick and place step during assembly. Therefore, the cost of the manufacturing apparatus is reduced and the cycle time is shortened.

【０００８】 （発明の実施形態の詳細な説明） 図１および図２は、従来技術のパワー半導体ダイ１０と、半田またはエポキシ
樹脂の付着材料１２によってダイが付着される導電性基板１１を示している。従
来法では、材料１２がこぼれ、それにより、所与の面積の基板上におけるダイの
最大サイズが限定されることに留意されたい。DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION FIGS. 1 and 2 show a prior art power semiconductor die 10 and a conductive substrate 11 to which the die is attached by solder or epoxy resin attachment material 12. There is. Note that in the conventional method, material 12 spills, which limits the maximum size of the die on a substrate of a given area.

【０００９】 図３および図４は、図１および図２のダイ１０を示しており、薄くて柔軟な接
着フィルム１３を用いてダイ１０および基板１１をボンディングしている。フィ
ルム１３は、導電性であるか、または絶縁性であることができ、熱硬化可能であ
る。図３および図４で見られるように、このようなフィルムを用いると、こぼれ
がなくなるので、図１および図２の基板と同じ面積の基板１１上で、より大きな
面積のダイ１０が可能になる。FIGS. 3 and 4 show the die 10 of FIGS. 1 and 2, in which a thin, flexible adhesive film 13 is used to bond the die 10 and the substrate 11. The film 13 can be electrically conductive or insulative and can be thermoset. As seen in FIGS. 3 and 4, the use of such a film eliminates spillage, thus allowing a larger area die 10 on a substrate 11 of the same area as the substrate of FIGS. 1 and 2. .

【００１０】 本発明の新規な方法は、図５から図８に示してある。図５は、従来の方法で同
時に加工される多数の同一のパワー半導体ダイを含む半導体デバイスウェーハ２
１を示している。したがって、ウェーハは、導電性ソース電極および底部導電性
ドレイン電極によって従来通り覆われた頂部表面にＰ／Ｎ接合を有する何百もの
同一の縦型導電パワーＭＯＳＦＥＴダイを含むことができる。ウェーハのダイは
、従来の切り分け装置（ｓａｗｉｎｇ ａｐｐａｒａｔｕｓ）でウェーハを切り
分けることによって、シンギュレーションされる。次に、ダイのドレイン電極を
基板に半田付けまたはエポキシボンディングすることによって、個々のダイをリ
ードフレームまたは他の基板上に装着する。The novel method of the present invention is shown in FIGS. FIG. 5 shows a semiconductor device wafer 2 including a number of identical power semiconductor dies that are simultaneously processed in a conventional manner.
1 is shown. Thus, the wafer can include hundreds of identical vertical conductive power MOSFET dies with a P / N junction on the top surface that is conventionally covered by a conductive source electrode and a bottom conductive drain electrode. The wafer die is singulated by slicing the wafer with a conventional shaving apparatus. The individual dies are then mounted on a leadframe or other substrate by soldering or epoxy bonding the die drain electrodes to the substrate.

【００１１】 本発明によれば、接着フィルム２０を、約６インチ（１５．２４ｃｍ）の典型
的な直径を有することができるウェーハのサイズに切り分ける。According to the present invention, the adhesive film 20 is cut into wafer sizes that can have a typical diameter of about 6 inches (15.24 cm).

【００１２】 フィルム２０は、好ましくは、ポリイミドフィルム、例えばＰＣボードや「フ
レックス」回路で電気巻線絶縁（ｅｌｅｃｔｒｉｃａｌ ｗｉｎｄｉｎｇ ｉｎ
ｓｕｌａｔｉｏｎ）など用にしばしば用いられる「ＫＡＰＴＯＮ」フィルムとし
て公知のポリイミドフィルムである。Ｋａｐｔｏｎポリイミドは優れた絶縁体で
ある。次に、ウェーハ２１およびフィルム２０を互いに積層し、予熱して接着力
を向上させるが、フィルム２０は、完全には硬化させない。The film 20 is preferably a polyimide film, such as a PC board or “flex” circuit for electrical winding in.
It is a polyimide film known as a "KAPTON" film, which is often used for the purposes such as the saturation. Kapton polyimide is a good insulator. The wafer 21 and the film 20 are then laminated together and preheated to improve adhesion, but the film 20 is not completely cured.

【００１３】 次に、図６に概略を示してあるように、フィルム２０およびウェーハ２１を同
時に切り代２２で切り分けて、別個のダイにする。従来のフレームまたは基板で
は、分離したフィルム／ダイのスタックを適所に保持する。次に、シンギュレー
ションされたデバイスが、自動的に取り上げられ、加熱された各リードフレーム
または基板上の装着すべき場所に運ばれるように、従来のピックアンドプレイス
デバイス（ｐｉｃｋ ａｎｄ ｐｌａｃｅ ｄｅｖｉｃｅ）中にスタックを配置
する。Next, as schematically shown in FIG. 6, the film 20 and the wafer 21 are simultaneously cut into a separate die 22 to form separate dies. Conventional frames or substrates hold the discrete film / die stacks in place. Then, in a conventional pick and place device, the singulated device is automatically picked up and carried to each heated lead frame or substrate where it should be mounted. Place the stack on.

【００１４】 すなわち、図７に示してあるように、従来のピックアンドプレイス装置によっ
て、ダイ／フィルムのスタック２１／２０を取り上げ、各基板１１上に配置する
ことができる。好ましくは、圧力を加えて、予熱された基板１１の表面上にスタ
ック２１／２０を押し付ける。That is, as shown in FIG. 7, a die / film stack 21/20 can be picked up and placed on each substrate 11 by a conventional pick and place apparatus. Preferably, pressure is applied to press the stack 21/20 onto the surface of the preheated substrate 11.

【００１５】 次に、ダイ／フィルムのスタック２１／２０と基板１１を約２６０℃まで加熱
して、フィルム２１を完全に熱硬化させ、基板１１に対するボンドを形成させる
。The die / film stack 21/20 and the substrate 11 are then heated to about 260 ° C. to fully thermoset the film 21 and form a bond to the substrate 11.

【００１６】 図７および図８のような構造化を行って、ダイオンダイパッケージ（ｄｉｅ−
ｏｎ−ｄｉｅ ｐａｃｋａｇｅ）（図９）またはサイドバイサイドダイパッケー
ジ（ｓｉｄｅ−ｂｙ−ｓｉｄｅ ｄｉｅ ｐａｃｋａｇｅ）（図１０）を形成す
ることもできる。すなわち、図９では、接着剤層２０と半導体ダイ２１とを有す
る２つの同一のダイ３０および３１を、ダイ３０の上にダイ３１を重ねて実装す
ることができる。ダイ３０および３１は、それぞれ、多種多様なデバイス、例え
ばＭＯＳＦＥＴおよびショットキーダイオードであってもよく、異なるサイズま
たは面積であってもよい。あるいは、ダイ３１は集積回路であってもよい。By structuring as shown in FIGS. 7 and 8, a dion die package (die-
An on-die package (FIG. 9) or a side-by-side die package (FIG. 10) can also be formed. That is, in FIG. 9, two identical dies 30 and 31 having the adhesive layer 20 and the semiconductor die 21 can be mounted on the die 30 with the die 31 stacked. The dies 30 and 31 may each be a wide variety of devices, such as MOSFETs and Schottky diodes, and may be of different sizes or areas. Alternatively, die 31 may be an integrated circuit.

【００１７】 さらに、図９における層２０は、ダイ３０と３１とを背面（ｂａｃｋ−ｔｏ−
ｂａｃｋ）接続させることのできる、適当な導電性接着フィルムとすることがで
きる。Further, the layer 20 in FIG. 9 has the dies 30 and 31 back-to-back.
back) It can be a suitable conductive adhesive film that can be connected.

【００１８】 図１０に示してあるように、ダイ３０および３１は、それぞれＭＯＳＦＥＴお
よびＩＣ（ダイ２１）を含んでいてもよい。As shown in FIG. 10, dies 30 and 31 may include MOSFETs and ICs (die 21), respectively.

【００１９】 フィルム２０用に使用できる他のフィルムとしては、Ａｌｐｈａ Ｍｅｔａｌ
ｓ ３８３Ｇ（ＲＨＳ）やＵＨ２Ｗ−Ｅポリイミドフィルム（ＬＨＳ）などの熱
可塑性接着剤ペーストが挙げられる。Other films that can be used for film 20 include Alpha Metal.
Examples include thermoplastic adhesive pastes such as s383G (RHS) and UH2W-E polyimide film (LHS).

【００２０】 本発明を、その特定の実施形態に関して説明したが、他の多くの変形形態およ
び改良および他の使用法も当業者には明らかとなるであろう。したがって、本発
明は本明細書における具体的な開示によってではなく、添付の特許請求の範囲に
よってのみ限定されることが好ましい。Although the present invention has been described with respect to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. Therefore, it is preferred that the present invention be limited not by the specific disclosure herein, but only by the appended claims.

【図面の簡単な説明】[Brief description of drawings]

【図１】 従来技術のダイ接着の上面図である。[Figure 1]   FIG. 3 is a top view of prior art die attachment.

【図２】 従来技術のダイ接着の側面図である。[Fig. 2]   FIG. 3 is a side view of die attachment of the prior art.

【図３】 導電性接着フィルムによって基板に接着されたパワー半導体ダイの上面図であ
る。FIG. 3 is a top view of a power semiconductor die bonded to a substrate by a conductive adhesive film.

【図４】 導電性接着フィルムによって基板に接着されたパワー半導体ダイの側面図であ
る。FIG. 4 is a side view of a power semiconductor die bonded to a substrate by a conductive adhesive film.

【図５】 大面積接着フィルムおよび半導体デバイスウェーハのシンギュレーション前の
透視図である。FIG. 5 is a perspective view of a large-area adhesive film and a semiconductor device wafer before singulation.

【図６】 接着後の図５の透視図である。[Figure 6]   FIG. 6 is a perspective view of FIG. 5 after bonding.

【図７】 基板に接着する前の図６のアセンブリからシンギュレーションされた１つのダ
イ／フィルムスタックを示す図である。FIG. 7 illustrates one die / film stack singulated from the assembly of FIG. 6 prior to bonding to a substrate.

【図８】 熱硬化およびボンディング後の図８のアセンブリを示す図である。[Figure 8]   FIG. 9 shows the assembly of FIG. 8 after thermosetting and bonding.

【図９】 ダイオンダイアセンブリ（ｄｉｅ−ｏｎ−ｄｉｅ ａｓｓｅｍｂｌｙ）に適用
される本発明の方法を示す図である。FIG. 9 illustrates the method of the present invention applied to a die-on-die assembly.

【図１０】 共通基板上におけるダイのサイドバイサイドアセンブリ（ｓｉｄｅ−ｂｙ−ｓ
ｉｄｅ ａｓｓｅｍｂｌｙ）に適用される本発明の方法を示す図である。FIG. 10 is a side-by-side assembly of dies on a common substrate.
FIG. 3 is a diagram showing the method of the present invention applied to the idea assembly).

───────────────────────────────────────────────────── フロントページの続き (81)指定国 ＥＰ(ＡＴ，ＢＥ，ＣＨ，ＣＹ， ＤＥ，ＤＫ，ＥＳ，ＦＩ，ＦＲ，ＧＢ，ＧＲ，ＩＥ，Ｉ Ｔ，ＬＵ，ＭＣ，ＮＬ，ＰＴ，ＳＥ，ＴＲ)，ＯＡ(ＢＦ ，ＢＪ，ＣＦ，ＣＧ，ＣＩ，ＣＭ，ＧＡ，ＧＮ，ＧＷ， ＭＬ，ＭＲ，ＮＥ，ＳＮ，ＴＤ，ＴＧ)，ＡＰ(ＧＨ，Ｇ Ｍ，ＫＥ，ＬＳ，ＭＷ，ＭＺ，ＳＤ，ＳＬ，ＳＺ，ＴＺ ，ＵＧ，ＺＷ)，ＥＡ(ＡＭ，ＡＺ，ＢＹ，ＫＧ，ＫＺ， ＭＤ，ＲＵ，ＴＪ，ＴＭ)，ＡＥ，ＡＧ，ＡＬ，ＡＭ， ＡＴ，ＡＵ，ＡＺ，ＢＡ，ＢＢ，ＢＧ，ＢＲ，ＢＹ，Ｂ Ｚ，ＣＡ，ＣＨ，ＣＮ，ＣＲ，ＣＵ，ＣＺ，ＤＥ，ＤＫ ，ＤＭ，ＤＺ，ＥＥ，ＥＳ，ＦＩ，ＧＢ，ＧＤ，ＧＥ， ＧＨ，ＧＭ，ＨＲ，ＨＵ，ＩＤ，ＩＬ，ＩＮ，ＩＳ，Ｊ Ｐ，ＫＥ，ＫＧ，ＫＰ，ＫＲ，ＫＺ，ＬＣ，ＬＫ，ＬＲ ，ＬＳ，ＬＴ，ＬＵ，ＬＶ，ＭＡ，ＭＤ，ＭＧ，ＭＫ， ＭＮ，ＭＷ，ＭＸ，ＭＺ，ＮＯ，ＮＺ，ＰＬ，ＰＴ，Ｒ Ｏ，ＲＵ，ＳＤ，ＳＥ，ＳＧ，ＳＩ，ＳＫ，ＳＬ，ＴＪ ，ＴＭ，ＴＲ，ＴＴ，ＴＺ，ＵＡ，ＵＧ，ＵＺ，ＶＮ， ＹＵ，ＺＡ，ＺＷ─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CR, CU, CZ, DE, DK , DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, J P, KE, KG, KP, KR, KZ, LC, LK, LR , LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, PT, R O, RU, SD, SE, SG, SI, SK, SL, TJ , TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW

Claims (11)

【特許請求の範囲】[Claims] 【請求項１】 半導体ダイを基板に接続する方法であって、 少なくとも部分的に硬化した第１の面積の薄くて柔軟な熱硬化性フィルムを、
複数の水平方向に変位され、かつ前記第１の面積に比べてそれぞれ実質的に小さ
い第３の面積を有する同一の半導体ダイを含む、第２の面積の薄い半導体ウェー
ハに接着させるステップと、 次に、前記熱硬化性フィルムと前記複数の同一である半導体ダイの両方を同時
にシンギュレーションして、それぞれが前記半導体ダイの面積、および前記半導
体ダイの１つの表面に接着させた接着フィルムの整合する面積を有する個々の素
子を形成するステップと、 次に、前記半導体ダイ上の前記熱硬化性フィルムを前記基板の頂部表面に押し
付け、前記シンギュレーションされた半導体ダイを前記基板の頂部表面に貼り付
けるステップと、 次に、前記熱硬化性フィルムを完全に硬化させて、前記半導体ダイを前記基板
に対して堅固に接着させるステップと を含むことを特徴とする方法。1. A method of connecting a semiconductor die to a substrate, the method comprising: an at least partially cured first area thin, flexible thermosetting film;
Bonding to a second area thin semiconductor wafer comprising a plurality of horizontally displaced and identical semiconductor dies each having a third area substantially smaller than said first area; And singulating both the thermosetting film and the plurality of identical semiconductor dies simultaneously, each aligning an area of the semiconductor die and an adhesive film adhered to one surface of the semiconductor die. Forming individual elements having an area of, and then pressing the thermosetting film on the semiconductor die against the top surface of the substrate, the singulated semiconductor die onto the top surface of the substrate. And a step of completely curing the thermosetting film to firmly adhere the semiconductor die to the substrate. Method characterized by including a flop. 【請求項２】 前記基板が、導体リードフレームであることを特徴とする請
求項１に記載の方法。2. The method of claim 1, wherein the substrate is a conductor leadframe. 【請求項３】 前記熱硬化性フィルムが、ポリイミドであることを特徴とす
る請求項１に記載の方法。3. The method of claim 1, wherein the thermosetting film is polyimide. 【請求項４】 前記熱硬化性フィルムが、ポリイミドであることを特徴とす
る請求項２に記載の方法。4. The method of claim 2, wherein the thermosetting film is polyimide. 【請求項５】 前記半導体ダイ上の前記熱硬化性フィルムが、前記基板上で
の組立て後に、前記半導体ダイの面積と同じ面積を有することを特徴とする請求
項１に記載の方法。5. The method of claim 1, wherein the thermosetting film on the semiconductor die has the same area as the area of the semiconductor die after assembly on the substrate. 【請求項６】 第２接着フィルムを有する第２半導体ダイを、前記第１半導
体ダイから水平方向に移動した位置で前記基板に接着させるステップを含むこと
を特徴とする請求項１に記載の方法。6. The method of claim 1 including the step of adhering a second semiconductor die having a second adhesive film to the substrate at a position horizontally displaced from the first semiconductor die. . 【請求項７】 その上に第２接着フィルムを有する第２半導体ダイを、前記
基板に固定された前記ダイの頂部に接着させるステップを含むことを特徴とする
請求項１に記載の方法。7. The method of claim 1 including the step of adhering a second semiconductor die having a second adhesive film thereon to the top of the die secured to the substrate. 【請求項８】 前記第１の面積が、前記第２の面積と実質的に同じであるこ
とを特徴とする請求項１に記載の方法。8. The method of claim 1, wherein the first area is substantially the same as the second area. 【請求項９】 前記半導体ダイおよびフィルムを、ピックアンドプレイス装
置によって前記基板へと移動させることを特徴とする請求項１に記載の方法。9. The method of claim 1, wherein the semiconductor die and film are moved to the substrate by a pick and place device. 【請求項１０】 前記接着フィルムが、前記半導体ダイの前記頂部表面に比
べてより小さい面積を有することを特徴とする請求項１に記載の方法。10. The method of claim 1, wherein the adhesive film has a smaller area compared to the top surface of the semiconductor die. 【請求項１１】 前記接着フィルムが、前記半導体ダイの前記頂部表面に比
べてより小さい面積を有し、前記第２半導体ダイと前記第２接着フィルムの両方
が、前記接着フィルムと同じ面積を有することを特徴とする請求項７に記載の方
法。11. The adhesive film has a smaller area compared to the top surface of the semiconductor die, and both the second semiconductor die and the second adhesive film have the same area as the adhesive film. The method according to claim 7, characterized in that
JP2001540836A 1999-11-24 2000-11-22 Power semiconductor die bonding method using conductive adhesive film Expired - Fee Related JP3771843B2 (en)

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TW501207B (en) 2002-09-01
WO2001039266A1 (en) 2001-05-31

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