JP2003533872A - Pre-apply die attach material to wafer backside - Google Patents

Pre-apply die attach material to wafer backside

Info

Publication number
JP2003533872A
JP2003533872A JP2001577607A JP2001577607A JP2003533872A JP 2003533872 A JP2003533872 A JP 2003533872A JP 2001577607 A JP2001577607 A JP 2001577607A JP 2001577607 A JP2001577607 A JP 2001577607A JP 2003533872 A JP2003533872 A JP 2003533872A
Authority
JP
Japan
Prior art keywords
die
attach material
wafer
surface area
die attach
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2001577607A
Other languages
Japanese (ja)
Inventor
フーング，サリー・ワイ・エル
ホ，コク・コーン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2003533872A publication Critical patent/JP2003533872A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

(57)【要約】 下部ダイのボンディングパッドの汚れをなくし、均一なボンド線厚さを提供する、積層ダイ構造の上部ダイを下部ダイにダイボンディングするための方法が提供されている。実施例は、上部ダイがまだウェハ形状である間に、ダイ付着材を積層ダイパッケージの上部ダイに、粘性形状のエポキシをウェハの裏面に回転させるかもしくはスクリーンを用いて付着させることによって、またはエポキシフィルムをウェハの裏面に貼り合せることによって、塗布することを含む。ウェハは次に切断テープ上に置かれ、上部ダイを含むダイに切断される。上部ダイはその後、下部ダイの上に置かれ、エポキシが硬化される。粘性のあるダイ付着材が下部ダイ上に堆積されないため、ダイ付着材は下部ダイのボンディングパッド上へと流れない。このため、上部ダイを下部ダイの上面に付着させる際に下部ダイのボンディング区域のみが露出されるように、下部ダイの大きさを縮小することが可能であり、それにより、積層ダイアセンブリの小型化が可能となる。また、上部ダイのダイ付着区域全体が予め定められた量のダイ付着材に覆われるため、上部ダイと下部ダイとの間のボンド線厚さを慎重に制御でき、信頼性が高まる。 SUMMARY A method is provided for die bonding an upper die of a stacked die structure to a lower die, which eliminates contamination of the lower die bond pads and provides a uniform bond line thickness. Examples are to attach the die attach material to the upper die of the stacked die package while the upper die is still in wafer shape, and to apply or apply a viscous shaped epoxy to the backside of the wafer by rotating or using a screen, or Including applying by attaching an epoxy film to the backside of the wafer. The wafer is then placed on a cutting tape and cut into dies, including the top die. The upper die is then placed on the lower die and the epoxy is cured. Because the viscous die attach material is not deposited on the lower die, the die attach material does not flow onto the bonding pads of the lower die. Therefore, it is possible to reduce the size of the lower die so that only the bonding area of the lower die is exposed when attaching the upper die to the upper surface of the lower die, thereby reducing the size of the stacked die assembly. Is possible. Also, because the entire die attach area of the upper die is covered with a predetermined amount of die attach material, the bond line thickness between the upper die and the lower die can be carefully controlled, increasing reliability.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の分野】FIELD OF THE INVENTION

この発明は、半導体パッケージングにおけるダイボンディングに関する。この
発明は、積層ダイパッケージング構造の製造において、特定の利用可能性を有す
る。The present invention relates to die bonding in semiconductor packaging. The invention has particular applicability in the manufacture of stacked die packaging structures.

【０００２】[0002]

【背景技術】[Background technology]

電子構成要素の小型化が益々要求されているため、「積層ダイ」パッケージと
して知られる半導体パッケージング構造が開発されてきた。従来の積層ダイパッ
ケージでは、フラッシュメモリデバイスなどの「ダイ」と呼ばれる第１の半導体
ベアチップが、エポキシ接着剤などを用いて、回路基板またはリードフレームな
どの基板に接合される。ＤＲＡＭなどの第２のダイが、第１のダイの上面に同様
に接合され、それによって必要とされる基板の表面積が小さくなる。両方のダイ
は、各ダイの露出された周辺領域に配置されたボンディングパッドに付着された
ワイヤボンドを介して、基板に電気的に接続されている。Due to the ever-increasing demand for smaller electronic components, semiconductor packaging structures known as "stacked die" packages have been developed. In a conventional stacked die package, a first semiconductor bare chip called a "die" such as a flash memory device is bonded to a circuit board or a substrate such as a lead frame using an epoxy adhesive or the like. A second die, such as a DRAM, is also bonded to the top surface of the first die, thereby reducing the substrate surface area required. Both dies are electrically connected to the substrate via wire bonds attached to bond pads located in the exposed peripheral areas of each die.

【０００３】 従来の積層ダイアセンブリ手法では、第２のダイは、測定された量のダイ付着
材、通常はエポキシペーストを第１のダイの上面に塗布することによって、第１
のダイの上面に接合される。第２のダイは次に、第１のダイの周辺ボンディング
パッドが第２のダイによって覆われないように、従来のダイボンダを用いて第１
のダイの上に置かれる。理想的には、エポキシは第２のダイの底面積を越えて広
がってはならず、こうして第１のダイのボンディングパッドの汚れが防止され、
同時に、予め定められたダイ付着材の厚さ（「ボンド線厚さ」と呼ばれる）が確
実となる。不十分なボンド線厚さは、完成デバイスの信頼性の低下に関連する。
したがって、エポキシを正確に置く必要があり、また、供給されるエポキシの量
を慎重に制御する必要がある。In conventional stacked die assembly techniques, the second die is first coated by applying a measured amount of die attach material, typically an epoxy paste, to the top surface of the first die.
Bonded to the top surface of the die. The second die is then first bonded using a conventional die bonder so that the peripheral bonding pads of the first die are not covered by the second die.
Placed on the die. Ideally, the epoxy should not extend beyond the bottom area of the second die, thus preventing fouling of the bonding pads of the first die,
At the same time, a predetermined die attach material thickness (called the "bond line thickness") is ensured. Poor bondline thickness is associated with reduced reliability of the finished device.
Therefore, the epoxy must be placed accurately and the amount of epoxy delivered must be carefully controlled.

【０００４】 不利なことには、エポキシペーストは、その粘性のある性質のため、プロセス
制御を慎重に行なっても、第２のダイの底面積を越えて第１のダイのボンディン
グパッド上へと広がりがちであり、そのため適切なワイヤボンディングを妨げる
。さらに、ボンド線厚さは通常、デバイスによって均一ではない。つまり、ボン
ド線厚さの変動は通常、１ミルよりも大きく、信頼性の問題を招く。これらの問
題を解決する従来のアプローチには、下部ダイの大きさを増大させてエポキシの
流れを受入れ、ボンディングパッドを汚さないようにすること、たとえば第１の
ダイの上面上のスペースを２倍または３倍にすることが含まれる。しかしこれは
、積層ダイアセンブリが占める貴重な「不動産」の量を増大させるため、好まし
くない。別のアプローチは、第２のダイを第１のダイに接合する前に、第２のダ
イの裏面にエポキシペーストを塗布することである。しかし、これによって第２
のダイの取扱いを増やす必要が生じ、それは第２のダイの上面に損傷をたやすく
与える恐れがあるので、完成デバイスの不良および／または信頼性問題をもたら
す。Disadvantageously, the viscous nature of the epoxy paste, even with careful process control, extends beyond the bottom area of the second die and onto the bonding pads of the first die. It tends to spread, thus preventing proper wire bonding. Moreover, bondline thickness is typically not uniform from device to device. That is, bond line thickness variations are typically greater than 1 mil, leading to reliability problems. A conventional approach to solving these problems is to increase the size of the bottom die to accept the epoxy flow and not contaminate the bond pads, eg double the space on the top surface of the first die. Or triple is included. However, this is undesirable because it increases the amount of valuable "real estate" occupied by the laminated die assembly. Another approach is to apply an epoxy paste to the backside of the second die before joining the second die to the first die. However, this
Additional die handling, which can easily damage the top surface of the second die, resulting in defective and / or reliability issues with the finished device.

【０００５】 ダイ付着材がボンディングパッドを汚すことを防止し、かつ、ボンド線厚さの
改良された制御を提供して、それにより完成デバイスの製造歩留りおよび信頼性
を高める、積層ダイパッケージ構造を組立てるための方法が必要とされている。A stacked die package structure that prevents the die attach material from soiling the bonding pads and provides improved control of bond line thickness, thereby increasing manufacturing yield and reliability of the finished device. A method for assembling is needed.

【０００６】[0006]

【発明の概要】[Outline of the Invention]

この発明の１つの利点は、下部ダイのボンディングパッドの汚れをなくし、均
一なボンド線厚さを提供する、積層ダイ構造の上部ダイを下部ダイにダイボンデ
ィングする方法である。One advantage of the present invention is a method of die bonding an upper die of a stacked die structure to a lower die that cleans the bonding pads of the lower die and provides a uniform bond line thickness.

【０００７】 この発明のさらなる利点および他の特徴は、一部は以下の説明に記載され、一
部は当業者が以下を検討すれば明らかとなり、またはこの発明の実践から習得さ
れるかも知れない。この発明の利点は、特許請求の範囲に特に指摘されるように
理解され、得られるかも知れない。Additional advantages and other features of the invention will be set forth in part in the description that follows, and in part will become apparent to those of ordinary skill in the art upon reviewing the following, or may be learned from practice of the invention. . The advantages of this invention may be realized and obtained as particularly pointed out in the appended claims.

【０００８】 この発明によれば、前述およびその他の利点は、上部半導体ダイを基板に付着
させるための方法によって部分的に達成され、この方法は、ダイ付着材を半導体
ウェハの裏面に塗布するステップと、切断テープをダイ付着材に付着させるステ
ップと、ウェハとダイ付着材とを切断して上部ダイを含む複数のダイを形成する
ステップと、基板の上に上部ダイを置くステップと、ダイ付着材を硬化させるス
テップとを含む。According to the present invention, the foregoing and other advantages are partially achieved by a method for attaching an upper semiconductor die to a substrate, the method comprising applying a die attach material to the backside of a semiconductor wafer. Attaching a cutting tape to the die attach material, cutting the wafer and the die attach material to form a plurality of dies including the upper die, placing the upper die on the substrate, and attaching the die. Curing the material.

【０００９】 この発明の別の局面は、上記方法に従って作られた半導体パッケージアセンブ
リである。Another aspect of the present invention is a semiconductor package assembly made according to the above method.

【００１０】 この発明のさらなる利点は、以下の詳細な説明から、当業者にはたやすく明ら
かとなるであろう。そこには、この発明の好ましい実施例のみが、単にこの発明
を実行するために考えられる最良の形態の例示によって示され、説明されている
。理解されるように、この発明は他の異なる実施例が可能であり、そのいくつか
の詳細は、この発明から全く逸脱せずに、さまざまな明らかな局面において変形
可能である。したがって、図面および説明は本質的に例示的なものであって制限
的なものではないと考えられるべきである。Further advantages of the invention will be readily apparent to those skilled in the art from the following detailed description. Only the preferred embodiments of the invention are shown and described therein, merely by way of illustration of the best mode contemplated for carrying out the invention. As will be appreciated, the invention is capable of other different embodiments, and its several details are capable of modifications in various obvious aspects, all without departing from the invention. Therefore, the drawings and description should be considered as illustrative in nature and not restrictive.

【００１１】 添付図面を参照するが、参照符号が同じ要素は、全体を通して同じ要素を表わ
している。Referring to the accompanying drawings, like elements having like reference numerals refer to like elements throughout.

【００１２】[0012]

【発明の説明】DESCRIPTION OF THE INVENTION

上部ダイ用の粘性のあるダイ付着材を下部ダイの上に塗布する、積層ダイパッ
ケージを組立てるための従来の方法では、下部ダイのボンディングパッドの汚れ
を避けるため、下部ダイは第１のダイよりも面積がかなり大きいものである必要
があり、それにより小型化が制限されている。また、従来の手法は、不十分かつ
均一ではないボンド線厚さをもたらし、それにより完成デバイスの信頼性に悪影
響を与える。この発明は、従来の製造工程から生じるこれらの問題に対処し、問
題を解決する。The conventional method for assembling a stacked die package, in which a viscous die attach material for the upper die is applied on top of the lower die, the lower die is better than the first die to avoid soiling the bonding pads of the lower die Must also be fairly large in area, which limits miniaturization. Also, conventional approaches result in inadequate and non-uniform bond line thickness, thereby adversely affecting the reliability of the finished device. The present invention addresses and solves these problems resulting from conventional manufacturing processes.

【００１３】 この発明の方法によれば、上部ダイがまだウェハ形状である間に、ダイ付着材
が積層ダイパッケージの上部ダイに、粘性形状のエポキシをウェハの裏面に回転
させるかもしくはスクリーンを用いて付着させることによって、またはエポキシ
フィルムをウェハの裏面に貼り合せることによって、塗布される。ウェハは次に
切断テープ上に置かれ、上部ダイを含むダイに切断される。上部ダイはその後、
下部ダイの上に置かれ、エポキシが硬化されて積層ダイアセンブリが完成する。
上部ダイがウェハ形状である間に上部ダイにダイ付着材を塗布することにより、
上部ダイのさらなる取扱いが回避され、上部ダイの上面への損傷が防止される。
さらに、粘性のあるダイ付着材が下部ダイ上に堆積されないため、この発明は、
ダイ付着材が下部ダイのボンディングパッド上へ流れる問題を排除する。このた
め、上部ダイを下部ダイの上面に付着させる際に下部ダイのボンディング区域の
みが露出されるように、下部ダイの大きさを縮小することが可能であり、それに
より、積層ダイアセンブリのさらなる小型化が可能となる。また、上部ダイのダ
イ付着区域全体が予め定められた量のダイ付着材に覆われるため、上部ダイと下
部ダイとの間のボンド線厚さを慎重に制御でき、信頼性が高まる。According to the method of the present invention, while the upper die is still in wafer form, the die attach material is used to rotate the viscous epoxy onto the backside of the wafer or to use a screen on the upper die of the stacked die package. Applied by depositing or by attaching an epoxy film to the backside of the wafer. The wafer is then placed on the cutting tape and cut into dies including the top die. The upper die is then
Placed on the bottom die and the epoxy is cured to complete the laminated die assembly.
By applying die attach material to the upper die while the upper die is in wafer form,
Further handling of the upper die is avoided and damage to the upper surface of the upper die is prevented.
In addition, because the viscous die attach material is not deposited on the lower die, the present invention provides
Eliminates the problem of die attach material flowing onto the bonding pads of the lower die. Therefore, it is possible to reduce the size of the lower die such that only the bonding area of the lower die is exposed when the upper die is attached to the upper surface of the lower die, thereby further increasing the stacking die assembly. Miniaturization is possible. In addition, since the entire die attachment area of the upper die is covered with a predetermined amount of die attachment material, the bond line thickness between the upper die and the lower die can be carefully controlled, and reliability is increased.

【００１４】 この発明の方法の一実施例を、図１Ａ−図１Ｆを参照して説明する。図１Ａに
示すように、約０．５ミルまたはそれ以下の厚さを有するエポキシなどの、予め
定められた厚さｔを有するダイ付着材１１０の層が、半導体ウェハ１００の裏面
１００ａに塗布される。ダイ付着材１１０は、好ましくは、日本の日立化成、ま
たは日本の住友から入手可能な、商業的に入手可能なＢステージのエポキシフィ
ルムなどの薄膜の形で貼付けられる。エポキシフィルムのダイ付着材層１１０は
、従来の貼り合せ装置を用いて、それを裏面１００ａと接触するように置き、次
に、それがウェハ１００に接着して空気がフィルムとウェハ１００との間に閉じ
込められないよう、熱と圧力とをローラなどで加えることによって、ウェハ１０
０の裏面１００ａに手動または自動で貼り合せられる。貼り合せの後、ダイ付着
材層１１０はウェハ１００の大きさにトリミングされる。One embodiment of the method of the present invention will be described with reference to FIGS. 1A-1F. As shown in FIG. 1A, a layer of die attach material 110 having a predetermined thickness t, such as epoxy having a thickness of about 0.5 mils or less, is applied to the backside 100a of the semiconductor wafer 100. It The die attach material 110 is preferably applied in the form of a thin film such as a commercially available B-stage epoxy film available from Hitachi Chemical of Japan or Sumitomo of Japan. The epoxy film die attach material layer 110 is placed using conventional bonding equipment such that it is in contact with the back surface 100a, which is then adhered to the wafer 100 to allow air to pass between the film and the wafer 100. By applying heat and pressure with a roller or the like so as not to be confined in the wafer 10,
The back surface 100a of No. 0 is attached manually or automatically. After bonding, the die attachment material layer 110 is trimmed to the size of the wafer 100.

【００１５】 この発明の代替的な一実施例では、ダイ付着材は、回転して層１１０を形成す
ることにより、裏面１００ａに粘性形状で塗布される。回転方法は、従来のウェ
ハ処理手法においてウェハ上面にＰｉコーティングを施すために用いられる真空
チャックなどの従来の回転タイプチャック内に、ウェハ１００を保持することを
含む。カリフォルニア州ランチョ・ドミンキエス（Rancho Dominquiez）のエイ
ブルスティックラボラトリーズ（Ablestik Laboratories）から入手可能である
ＲＰ５９８−３Ｂなどの粘性のあるダイ付着材が、ウェハ１００の裏面１００ａ
の中央に堆積され、チャックの回転がダイ付着材をウェハ１００の縁へと広げる
。回転速度、堆積されるダイ付着材の量、およびダイ付着材の配合が、ダイ付着
材層１１０の厚さｔを決定する。In an alternative embodiment of the invention, the die attach material is applied in a viscous shape to the back surface 100a by spinning to form the layer 110. The spinning method involves holding the wafer 100 in a conventional spinning-type chuck, such as a vacuum chuck used to apply a Pi coating on the upper surface of the wafer in conventional wafer processing techniques. A viscous die attach material, such as RP598-3B available from Ablestik Laboratories of Rancho Dominquiez, Calif., Is used for the backside 100a of wafer 100.
, The rotation of the chuck spreads the die attach material to the edge of the wafer 100. The rotational speed, the amount of die attach material deposited, and the die attach material formulation determine the thickness t of the die attach material layer 110.

【００１６】 この発明の別の代替的な実施例では、ダイ付着材は、スクリーンを用いて層１
１０を形成することにより、裏面１００ａに粘性形状で塗布される。スクリーン
を用いる方法では、カリフォルニア州ランチョ・ドミンキエスのエイブルスティ
ックラボラトリーズから入手可能であるＲＰ５９８−３Ｂなどの粘性のあるダイ
付着材が、従来のスクリーンを用いる手法に使用されるような目が細かいスクリ
ーンの上に置かれる。スクリーンはウェハ１００の裏面１００ａと接触するよう
に置かれ、ダイ付着材は「スキージをかけられ」て裏面１００ａ全体に広がり、
その結果、予め定められた厚さｔを有するダイ付着材層１１０が形成される。In another alternative embodiment of the invention, the die attach material is screened using a layer 1
By forming 10, the back surface 100a is applied in a viscous shape. In a screen-based method, a viscous die attach material such as RP598-3B, available from Able Stick Laboratories of Rancho Dominkies, Calif. Placed on top. The screen is placed in contact with the backside 100a of the wafer 100 and the die attach material is "squeegeeed" and spreads across the backside 100a,
As a result, the die attachment material layer 110 having a predetermined thickness t is formed.

【００１７】 図１Ｂを参照すると、ダイ付着材層１１０が塗布された後、従来の切断テープ
１２０が従来の手法を用いてダイ付着材層１１０に付着される。ウェハ１００と
ダイ付着材１１０とは次に、切断テープ１２０が図１Ｃに示すように損傷を受け
ないよう、従来の方法で切断され、各々が表面区域ａ1（図１Ｄ参照）を有する
複数のダイＤが形成される。次に、切断されたウェハ１００は従来のダイボンダ
へと運ばれ、そこでダイＤは、切断テープ１２０の下から押し上げる針などによ
って、切断テープ１２０から放出される。ダイＤは次に真空チャックを用いてつ
まみ上げられ、積層ダイパッケージ（図１Ｅ参照）の下部ダイ１３０などの基板
の上に置かれる。Referring to FIG. 1B, after the die attach material layer 110 is applied, a conventional cutting tape 120 is attached to the die attach material layer 110 using conventional techniques. The wafer 100 and die attach material 110 are then cut in a conventional manner so that the cutting tape 120 is not damaged as shown in FIG. 1C, each having a plurality of surface areas a 1 (see FIG. 1D). Die D is formed. The cut wafer 100 is then transferred to a conventional die bonder, where the die D is ejected from the cutting tape 120, such as by a needle pushing up from under the cutting tape 120. The die D is then picked up using a vacuum chuck and placed on a substrate such as the bottom die 130 of the stacked die package (see FIG. 1E).

【００１８】 図１Ｆを参照すると、下部ダイ１３０は、好ましくは、周辺ボンディング区域
１３０ａと、ダイＤの表面区域ａ1にほぼ等しい中央表面区域１３０ｂとからな
る表面区域を有する。ダイＤは、好ましくは、上部ダイ表面区域ａ1と中央表面
区域１３０ｂとが実質的に整列されるように、下部ダイ１３０の上に置かれる。
このため、ダイＤを下部ダイ１３０の上に置いた場合、ボンディング区域１３０
ａのみが露出される。ダイＤが下部ダイ１３０の上に置かれた後、ダイ付着材層
１１０は、好ましくは、下部ダイ１３０とダイＤとをダイボンダでヒータブロッ
クなどにより加熱してダイ付着材層１１０を部分的に硬化させ、次に従来の硬化
炉内で層１１０を完全に硬化させることによって、硬化される。Referring to FIG. 1F, the lower die 130 preferably has a surface area consisting of a peripheral bonding area 130a and a central surface area 130b that is approximately equal to the surface area a 1 of die D. The die D is preferably placed on the lower die 130 such that the upper die surface area a 1 and the central surface area 130b are substantially aligned.
Therefore, when the die D is placed on the lower die 130, the bonding area 130
Only a is exposed. After the die D is placed on the lower die 130, the die attach material layer 110 is preferably partially heated by heating the lower die 130 and the die D by a heater block or the like with a die bonder. It is cured by curing and then fully curing layer 110 in a conventional curing oven.

【００１９】 この発明は、ダイ付着材層１１０をウェハ１００にフィルムとして、またはス
クリーンを用いるかもしくは回転させることによって事前塗布することにより、
ダイ付着材１１０がボンディング区域１３０ａ上へ流れる可能性を排除しており
、それによって歩留りを向上させ、下部ダイ１３０の大きさが最適化される（つ
まり最小化される）ことを可能にする。言い換えれば、上部ダイと下部ダイとを
積層した際に下部ダイのボンディング区域１３０ａのみが露出されるように、下
部ダイの大きさを調整することができる。さらに、事前塗布されるダイ付着材層
１１０の厚さが慎重に制御されるため、均一な、予め定められたボンド線厚さｔ
が達成され（図１Ｅ参照）、それによって完成積層ダイパッケージの信頼性が向
上する。また、ウェハ形状のデバイスにダイ付着材を事前塗布することにより、
スループットが増加し、コストが削減される。The present invention provides that the die attach material layer 110 is pre-applied to the wafer 100 as a film, or by using or rotating a screen,
It eliminates the possibility of die attach material 110 flowing onto bonding area 130a, thereby improving yield and allowing the size of lower die 130 to be optimized (ie, minimized). In other words, the size of the lower die can be adjusted so that only the bonding area 130a of the lower die is exposed when the upper die and the lower die are stacked. Moreover, the thickness of the pre-applied die attach material layer 110 is carefully controlled so that a uniform, predetermined bond line thickness t.
(See FIG. 1E), which improves the reliability of the finished stacked die package. In addition, by pre-applying the die attachment material to the wafer-shaped device,
Throughput is increased and costs are reduced.

【００２０】 この発明の一実施例に従って作られた半導体パッケージアセンブリが、図２Ａ
および図２Ｂに示されている。下部半導体ダイ２２０は、プリント回路基板など
の基板２００に、エポキシなどの第１のダイ付着材層２１０によって付着されて
いる。上部半導体ダイ２４０は、下部ダイ２２０の上面に、予め定められた厚さ
ｔを有する第２のエポキシダイ付着材層２３０によって付着されている。上部半
導体ダイ２４０は表面区域ａ1を有し、下部半導体ダイ２２０は、周辺ボンディ
ング区域ａ2と、上部ダイ表面区域ａ1にほぼ等しい中央表面区域ａ3とからなる
表面区域を有する。上部ダイ２４０は、上部ダイ表面区域ａ1と中央表面区域ａ3 とが実質的に整列され、実質的に周辺ボンディングパッド区域ａ2のみが露出さ
れるように、下部ダイ２２０に付着される。このため、下部ダイ２２０の大きさ
は最小化される。A semiconductor package assembly made in accordance with one embodiment of the present invention is shown in FIG.
And shown in FIG. 2B. The lower semiconductor die 220 is attached to a substrate 200, such as a printed circuit board, by a first die attach material layer 210, such as epoxy. The upper semiconductor die 240 is attached to the upper surface of the lower die 220 by a second epoxy die attach material layer 230 having a predetermined thickness t. The upper semiconductor die 240 has a surface area a 1 and the lower semiconductor die 220 has a surface area consisting of a peripheral bonding area a 2 and a central surface area a 3 approximately equal to the upper die surface area a 1 . The upper die 240 is attached to the lower die 220 such that the upper die surface area a 1 and the central surface area a 3 are substantially aligned and substantially only the peripheral bonding pad area a 2 is exposed. Therefore, the size of the lower die 220 is minimized.

【００２１】 この発明は、さまざまな種類の半導体パッケージング構造の製造に利用可能で
ある。この発明の方法は、スペースおよび／またはボンド線厚さを考慮すべきあ
らゆるダイボンディング用途に使用可能である。たとえば、この発明は、上部ダ
イを下部ダイに接合するためだけでなく、積層ダイパッケージの下部ダイを回路
基板に接合するためにも使用できる。The present invention can be used in the manufacture of various types of semiconductor packaging structures. The method of the present invention can be used in any die bonding application where space and / or bond line thickness is a consideration. For example, the invention can be used not only to bond the top die to the bottom die, but also to bond the bottom die of the stacked die package to the circuit board.

【００２２】 この発明は、従来の材料、方法、および装置を採用することにより実践可能で
ある。したがって、そのような材料、装置および方法の詳細は、ここには詳細に
は記載されない。前述の説明には、この発明の完全なる理解を提供するため、特
定の材料、構造、化学物質、プロセスなどの多数の特定の詳細が記載されている
。しかし、この発明は具体的に記載された詳細に頼ることなく実践可能であるこ
とが認識されるべきである。他の点では、この発明を不必要に不明瞭にしないた
め、周知の処理構成は詳細には記載されていない。The present invention can be practiced by employing conventional materials, methods, and devices. Therefore, details of such materials, devices and methods are not described in detail here. In the foregoing description, numerous specific details are set forth, such as specific materials, structures, chemicals, processes, etc., in order to provide a thorough understanding of the present invention. However, it should be appreciated that this invention may be practiced without resorting to the details specifically set forth. In other respects, well-known processing arrangements have not been described in detail so as not to unnecessarily obscure the present invention.

【００２３】 この開示には、この発明の好ましい実施例およびその汎用性のほんの少数の例
のみが示され、記載されている。この発明はさまざまな他の組合せおよび環境で
使用可能であり、ここに表わされたようなこの発明の概念の範囲内で変更または
変形が可能である、ということを理解されたい。In this disclosure, there are shown and described only preferred embodiments of the invention and but a few examples of its versatility. It is to be understood that this invention can be used in various other combinations and environments, and can be modified or varied within the scope of the inventive concept as expressed herein.

【図面の簡単な説明】[Brief description of drawings]

【図１Ａ】 この発明の一実施例に従った方法の一段階を概略的に示す図で
ある。FIG. 1A is a schematic illustration of a step in a method in accordance with an embodiment of the present invention.

【図１Ｂ】 この発明の一実施例に従った方法の一段階を概略的に示す図で
ある。FIG. 1B is a schematic diagram of a step in a method in accordance with an embodiment of the present invention.

【図１Ｃ】 この発明の一実施例に従った方法の一段階を概略的に示す図で
ある。FIG. 1C is a schematic diagram of a step in a method in accordance with an embodiment of the present invention.

【図１Ｄ】 この発明の一実施例に従った方法の一段階を概略的に示す図で
ある。FIG. 1D is a schematic diagram of a step in a method in accordance with an embodiment of the present invention.

【図１Ｅ】 この発明の一実施例に従った方法の一段階を概略的に示す図で
ある。FIG. 1E is a schematic illustration of a step in a method in accordance with an embodiment of the present invention.

【図１Ｆ】 この発明の一実施例に従った方法の一段階を概略的に示す図で
ある。FIG. 1F is a schematic diagram of a step in a method in accordance with an embodiment of the present invention.

【図２Ａ】 この発明の一実施例に従った半導体パッケージアセンブリの側
面図である。FIG. 2A is a side view of a semiconductor package assembly according to one embodiment of the present invention.

【図２Ｂ】 この発明の一実施例に従った半導体パッケージアセンブリの平
面図である。FIG. 2B is a plan view of a semiconductor package assembly according to one embodiment of the present invention.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 フーング，サリー・ワイ・エル アメリカ合衆国、95035 カリフォルニア 州、ミルピタス、ヨセミテ・ドライブ、 1884 (72)発明者 ホ，コク・コーン マレイシア、11950 ペナン、バヤン・バ ル、メダン・マヤンパシル、70 Ｆターム(参考） 5F047 BA33 BB11 BB19 【要約の続き】 ダイとの間のボンド線厚さを慎重に制御でき、信頼性が 高まる。─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hung, Sally Wy El             United States, 95035 California             State, Milpitas, Yosemite Drive,             1884 (72) Inventor Ho, Koku Korn             Malaysia, 11950 Penang, Bayan Ba             Le, Medan Mayanpasil, 70 F term (reference) 5F047 BA33 BB11 BB19 [Continued summary] The bond line thickness to and from the die can be carefully controlled for reliability Increase.

Claims (12)

【特許請求の範囲】[Claims] 【請求項１】 上部半導体ダイを基板に付着させるための方法であって、 ダイ付着材を半導体ウェハの裏面に塗布するステップと、 切断テープをダイ付着材に付着させるステップと、 ウェハとダイ付着材とを切断して複数のダイを形成するステップとを含み、複
数のダイは上部ダイを含み、前記方法はさらに、 基板の上に上部ダイを置くステップと、 ダイ付着材を硬化させるステップとを含む、方法。1. A method for attaching an upper semiconductor die to a substrate, the method comprising: applying a die attach material to the backside of a semiconductor wafer; attaching a cutting tape to the die attach material; and attaching the wafer and the die. Cutting the material to form a plurality of dies, the plurality of dies including a top die, the method further comprising: placing the top die on the substrate; and curing the die attach material. Including the method. 【請求項２】 ダイ付着材を塗布するステップは、ダイ付着材からなるフィ
ルムをウェハの裏面に貼り合せるステップを含む、請求項１に記載の方法。2. The method of claim 1, wherein applying the die attach material comprises laminating a film of die attach material to the backside of the wafer. 【請求項３】 貼り合せるステップは、 フィルムをウェハの裏面に接触するように置くステップと、 ウェハを加熱するステップと、 フィルムに圧力を加えるステップとを含む、請求項２に記載の方法。3. The step of laminating comprises:   Placing the film in contact with the backside of the wafer,   Heating the wafer,   Applying pressure to the film. 【請求項４】 貼り合せた後でウェハ周辺のフィルムを切るステップを含む
、請求項２に記載の方法。4. The method of claim 2 including the step of cutting the film around the wafer after laminating. 【請求項５】 ダイ付着材を塗布するステップは、ダイ付着材をウェハの裏
面上へ回転させて付着させるステップを含む、請求項１に記載の方法。5. The method of claim 1, wherein applying the die attach material comprises rotating the die attach material onto the backside of the wafer to deposit. 【請求項６】 ダイ付着材を塗布するステップは、ダイ付着材をウェハの裏
面上へスクリーンを用いて付着させるステップを含む、請求項１に記載の方法。6. The method of claim 1, wherein applying the die attach material comprises screen depositing the die attach material onto the backside of the wafer. 【請求項７】 上部ダイは表面区域を有し、基板は、周辺ボンディング区域
と、上部ダイの表面区域にほぼ等しい中央表面区域とからなる表面区域を有する
下部半導体ダイであり、前記方法は、上部ダイの表面区域と中央表面区域とが実
質的に整列され、周辺ボンディング区域が露出されるように、上部ダイを下部ダ
イの上に置くステップを含む、請求項１に記載の方法。7. The upper die has a surface area and the substrate is a lower semiconductor die having a surface area consisting of a peripheral bonding area and a central surface area approximately equal to the surface area of the upper die, the method comprising: The method of claim 1 including placing the upper die on the lower die such that the surface area of the upper die and the central surface area are substantially aligned and the peripheral bonding area is exposed. 【請求項８】 請求項７の方法によって作られた製品。8. A product made by the method of claim 7. 【請求項９】 上部ダイはダイボンダで基板の上に置かれ、硬化させるステ
ップは、 基板と上部ダイとをダイボンダで加熱し、ダイ付着材を部分的に硬化させるス
テップと、 基板と上部ダイとを硬化炉内で加熱し、ダイ付着材を完全に硬化させるステッ
プとを含む、請求項１に記載の方法。9. The upper die is placed on the substrate with a die bonder, and the curing step includes the steps of heating the substrate and the upper die with the die bonder to partially cure the die attach material, and the substrate and the upper die. Heating in a curing oven to completely cure the die attach material. 【請求項１０】 半導体パッケージアセンブリであって、 表面区域を有する上部半導体ダイと、 周辺ボンディング区域と中央表面区域とからなる表面区域を有する下部半導体
ダイとを含み、中央表面区域は上部ダイの表面区域にほぼ等しく、 上部ダイは、上部ダイの表面区域と中央表面区域とが実質的に整列され、周辺
ボンディング区域が露出されるように、下部ダイの上に付着される、半導体パッ
ケージアセンブリ。10. A semiconductor package assembly, comprising: an upper semiconductor die having a surface area and a lower semiconductor die having a surface area consisting of a peripheral bonding area and a central surface area, the central surface area being the surface of the upper die. A semiconductor package assembly, wherein the top die is deposited over the bottom die such that the surface area of the top die and the center surface area are substantially aligned and the peripheral bonding area is exposed. 【請求項１１】 基板をさらに含み、下部ダイは基板に付着されている、請
求項１０に記載のパッケージアセンブリ。11. The package assembly of claim 10, further comprising a substrate, the lower die attached to the substrate. 【請求項１２】 上部ダイと下部ダイとの間に予め定められた厚さを有する
ダイ付着材層を含む、請求項１０に記載のパッケージアセンブリ。12. The package assembly of claim 10, including a die attach material layer having a predetermined thickness between the upper die and the lower die.
JP2001577607A 2000-04-17 2000-11-17 Pre-apply die attach material to wafer backside Withdrawn JP2003533872A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US55162400A 2000-04-17 2000-04-17
US09/551,624 2000-04-17
PCT/US2000/031800 WO2001080312A1 (en) 2000-04-17 2000-11-17 Pre-application of die attach material to wafer back

Publications (1)

Publication Number Publication Date
JP2003533872A true JP2003533872A (en) 2003-11-11

Family

ID=24202024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001577607A Withdrawn JP2003533872A (en) 2000-04-17 2000-11-17 Pre-apply die attach material to wafer backside

Country Status (5)

Country Link
JP (1) JP2003533872A (en)
KR (1) KR20020089492A (en)
CN (1) CN1452786A (en)
TW (1) TW486788B (en)
WO (1) WO2001080312A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311727A (en) * 2006-05-22 2007-11-29 Sumitomo Bakelite Co Ltd Manufacturing method of semiconductor element and of semiconductor package
US10090278B2 (en) 2016-02-18 2018-10-02 Samsung Electronics Co., Ltd. Semiconductor packages

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7851916B2 (en) * 2005-03-17 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Strain silicon wafer with a crystal orientation (100) in flip chip BGA package
US7422707B2 (en) 2007-01-10 2008-09-09 National Starch And Chemical Investment Holding Corporation Highly conductive composition for wafer coating

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4688075A (en) * 1983-07-22 1987-08-18 Fairchild Semiconductor Corporation Integrated circuit having a pre-attached conductive mounting media and method of making the same
US4687693A (en) * 1985-06-13 1987-08-18 Stauffer Chemical Company Adhesively mountable die attach film
JPH04247640A (en) * 1991-02-04 1992-09-03 Matsushita Electron Corp Manufacture of semiconductor device
WO1993023982A1 (en) * 1992-05-11 1993-11-25 Nchip, Inc. Stacked devices for multichip modules
US5422435A (en) * 1992-05-22 1995-06-06 National Semiconductor Corporation Stacked multi-chip modules and method of manufacturing
WO1996013066A1 (en) * 1994-10-20 1996-05-02 National Semiconductor Corporation Method of attaching integrated circuit dies by rolling adhesives onto semiconductor wafers

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007311727A (en) * 2006-05-22 2007-11-29 Sumitomo Bakelite Co Ltd Manufacturing method of semiconductor element and of semiconductor package
US10090278B2 (en) 2016-02-18 2018-10-02 Samsung Electronics Co., Ltd. Semiconductor packages
US10651154B2 (en) 2016-02-18 2020-05-12 Samsung Electronics Co., Ltd. Semiconductor packages

Also Published As

Publication number Publication date
CN1452786A (en) 2003-10-29
WO2001080312A1 (en) 2001-10-25
KR20020089492A (en) 2002-11-29
TW486788B (en) 2002-05-11

Similar Documents

Publication Publication Date Title
JP4261356B2 (en) Method for manufacturing a semiconductor package
TWI305410B (en) Multi-chip package structure
TW546795B (en) Multichip module and manufacturing method thereof
CN105742198B (en) Die bonder and its application method
KR101475467B1 (en) Semiconductor die having a redistribution layer
US6703075B1 (en) Wafer treating method for making adhesive dies
TWI705524B (en) Semiconductor manufacturing device, semiconductor device manufacturing method and chuck
TW200409252A (en) Packaging process for improving effective die-bonding area
TW525275B (en) Semiconductor device and method of manufacturing same
JP2003533872A (en) Pre-apply die attach material to wafer backside
JP2002256238A (en) Adhesive film, method for producing semiconductor device using the same and semiconductor device
JPH11219962A (en) Manufacture of semiconductor device
JP2002256239A (en) Adhesive film, method for producing semiconductor device using the same and semiconductor device
JP4774999B2 (en) Manufacturing method of semiconductor device
US20060137420A1 (en) Process applied to semiconductor
US7498202B2 (en) Method for die attaching
US20080308915A1 (en) Chip package
JP3771843B2 (en) Power semiconductor die bonding method using conductive adhesive film
TWI240392B (en) Process for packaging and stacking multiple chips with the same size
CN107644843B (en) Wafer stack manufacturing method
TWI250597B (en) Method for manufacturing multi-chip package having encapsulated bond-wires between stack chips
JP2004079597A (en) Working method of semiconductor chip
TW201013874A (en) Chip package
TW457654B (en) Method for die attach
TWI225294B (en) Semiconductor chip package and method for manufacturing thereof

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20080205