JP2005129912A - Method for supplying passive element, passive element for semiconductor package production, and passive element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for supplying resistors/capacitors optimized for producing a semiconductor package incorporating a plurality of semiconductor package substrates and resistors/capacitors. <P>SOLUTION: In an assembly of resistors/capacitors formed on a ceramic substrate or silicon substrate having a controlled thickness, a surface on which the resistors/capacitors are not formed is ground as needed, so that thickness is reduced; and the assembly is adhered on a dicing tape and formed into individual pieces and then supplied; thereby supplying resistors/capacitors that do not so much limit design and production of semiconductor package. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a supply method in manufacturing a semiconductor package of passive elements such as resistors and capacitors constituting an electronic circuit. The present invention also relates to a passive element for manufacturing a semiconductor package for use in such a supply method, and more particularly to a passive element for manufacturing a semiconductor package that is used in a purpose of being singulated and placed in a semiconductor package. The present invention also relates to a passive element obtained by singulating the passive element for manufacturing a semiconductor package.

  As information communication devices such as mobile phones and portable personal computers have become smaller and more sophisticated, the semiconductors used in the devices have been changed from conventional lead frame packages to BGA (Ball Grid Array) and CSP (Chip Size Package). Such a non-lead frame package, and further, MCP (multi-chip package) in which a plurality of semiconductor chips are integrated in one semiconductor package, are becoming smaller and more functional. In addition, the trend of miniaturization is to resistors and capacitors, and miniaturization has progressed from 1608 size to 1005 size and further to 0603 size, and extremely small products such as 0402 size have been manufactured as a test. However, the reduction of the area occupied by resistors and capacitors is slow compared to semiconductors that can reduce the chip size by using nano-level wiring and stack multiple chips inside the semiconductor package. It is expected to become a hindrance to downsizing.

However, further miniaturization of resistors and capacitors is considered impractical in terms of manufacturing yield and handling, and a method of creating resistors and capacitors inside a printed wiring board (Patent Document 1) and a semiconductor package A method (Patent Document 2) in which a resistor and a capacitor are built in has been proposed. In particular, the method built in the semiconductor package is attracting attention as a superior technology because it can use resistors and capacitors that have been manufactured with established technology and have been guaranteed quality. In addition, the supply form of resistors and capacitors has been optimized in a form suitable for SMT (surface mount technology), and there is a problem that the compatibility with the semiconductor package manufacturing process is low.
Japanese Patent Laid-Open No. 9-2104090 Japanese Patent Laid-Open No. 10-176751

  An object of the present invention is to provide a passive element for a semiconductor package optimized for miniaturization and high functionality of an electronic device, a method for supplying a passive element when the passive element is arranged in a semiconductor package, and the supply method. The present invention provides a passive element for manufacturing a semiconductor package suitable for the above.

  By supplying the same resistor and capacitor to the positioning mounting device in a state where the same resistor and capacitor are aligned on the adhesive tape, the present inventors have increased compatibility with the semiconductor package manufacturing process and have been made thinner. It has been found that resistors and capacitors can be easily handled, and the present invention has been completed.

That is, the present invention
[1] A method of supplying resistors and / or capacitors constituting an electronic circuit, wherein a plurality of resistors and / or capacitors are arranged and arranged on an adhesive tape and supplied to a positioning and mounting device. A resistor and / or capacitor supply method,
[2] After a plurality of the same resistors and / or the same capacitors are arranged on the adhesive tape as an aggregate, they are cut on the adhesive tape and separated into resistors and / or capacitors. 1] The resistor and / or capacitor supply method according to item
[3] The resistor and / or capacitor supply method according to [2], wherein the singulated resistor and / or capacitor is a single resistor and / or capacitor,
[4] The resistor and / or capacitor supply method according to [2], wherein the separated resistors and / or capacitors are a plurality of the same resistors and / or the same capacitors,
[5] The resistor and / or capacitor supply method according to any one of [1] to [4], wherein the thickness of the resistor and / or capacitor is 50 μm or more and 150 μm or less,
[6] The resistor and / or capacitor supply method according to any one of items [1] to [5], wherein a terminal surface of the resistor and / or capacitor is covered with solder or tin.
[7] The resistor and / or capacitor supply method according to any one of [1] to [5], wherein a terminal surface of the resistor and / or capacitor is coated with gold,
[8] A semiconductor device manufactured using the resistor and / or capacitor supplied by the supply method according to any one of items [1] to [7].

  Specifically, in the method for supplying passive elements according to the present invention, the assembly in which the passive elements are arranged is thinned, the aggregate after thinning is separated into individual pieces, and the separated passive elements are processed. This is supplied to a semiconductor package manufacturing apparatus.

With such a configuration, it is possible to design the handling of the passive element so that the affinity of the passive element to the semiconductor package manufacturing process is high, and the passive element supply method that is optimized for downsizing and high functionality of electronic equipment Will be able to provide.
Further, by introducing the passive element into the semiconductor package manufacturing apparatus after thinning the passive element, the passive element can be handled more easily. Furthermore, it becomes possible to hold a plurality of passive elements as an aggregate and to transport and process them at the same time, so that the passive elements can be handled more easily when supplying the passive elements in the semiconductor package manufacturing process. become.

  In this passive element supply method, the singulation process can be performed by dicing the assembly stuck on the adhesive base material to which the film-like adhesive is stuck to separate the passive elements. Further, the film-like adhesive can be attached to the aggregate after the aggregate has been thinned. Moreover, you may make it the passive element separated into pieces supply to the positioning mounting apparatus of a passive element in the state in which the film-like adhesive material is affixed.

  With such a configuration, the film-like adhesive can be cured by high heat treatment performed in a normal process of the passive element, and the passive element can be firmly bonded, while the passive element is handled as an aggregate. Therefore, the passive element can be designed to have a high affinity for the semiconductor package manufacturing process, and a passive element supply method optimized for downsizing and high functionality of electronic devices can be provided. .

In the passive element supply method, the terminal surface of the passive element may be covered with solder or tin.
As a result, when the semiconductor package is formed, the terminals of the passive elements can be electrically joined to the substrate constituting the semiconductor device by soldering.

In the passive element supply method, the terminal surface of the passive element may be covered with gold.
Thereby, when forming the semiconductor package, the terminals of the passive elements can be electrically joined to the substrate constituting the semiconductor device by a technique such as a wire bonding method or a stud bump bonding method.

  The passive element for manufacturing a semiconductor package according to the present invention is obtained by thinning an assembly in which passive elements are aligned.

  This passive element for manufacturing a semiconductor package may be stuck on an adhesive substrate to which a film-like adhesive is stuck.

  In the passive element for manufacturing a semiconductor package, the terminal surface of each passive element may be covered with solder or tin, or may be covered with gold.

  The passive element according to the present invention is obtained by singulating one of the above-described passive elements for manufacturing a semiconductor package.

  According to the present invention, a semiconductor package incorporating a resistor and a capacitor and a plurality of semiconductor package substrates can be efficiently manufactured.

Hereinafter, embodiments of a passive element and a method for supplying a passive element to a semiconductor package according to the present invention will be described in detail with reference to the drawings.
In the description of the drawings, the same reference numerals are assigned to the same elements, and duplicate descriptions are omitted.

(Passive element supply method)
1 and 2 are process diagrams showing an embodiment of a passive element supply method for supplying a semiconductor package using a passive element for manufacturing a semiconductor package of the present invention.

  According to the present invention, the same or different passive elements such as resistors and / or capacitors are arranged on an adhesive tape and supplied to a positioning and mounting device used in a semiconductor package manufacturing process.

  As shown in FIG. 1A, a plurality of passive elements 10 are arranged in alignment on a substrate 19 such as a ceramic substrate or a silicon substrate that serves as a support. Affixed to the holding adhesive tape 60. Subsequently, as shown in FIG. 1 (b), the substrate 19 is ground with a rotating grindstone 62 until a predetermined thickness is obtained, and a plurality of passive elements are arranged and arranged as shown in FIG. 1 (c). Thus, an assembly 20 that is a passive element for manufacturing a semiconductor package is obtained.

  Further, as shown in FIG. 2B, the assembly 20 of passive elements shown in FIG. 2A is affixed to the ring-shaped jig 66 in order to enhance the compatibility with the semiconductor package manufacturing process. By this, it is affixed on the adhesive tape 64 which is an adhesive substrate to which an appropriate tension is applied. In addition, as the adhesive tape 64, a dicing film, a dicing die attach film, etc. are mentioned.

  Conventionally, individualized passive elements have been handled, and it has been difficult to apply to semiconductor package manufacturing processes, so there were cases where the efficiency of processes such as placement of passive elements was poor. By applying the assembly of elements to means normally used in a semiconductor package manufacturing process such as a dicing film or a dicing die attach film, it is possible to handle passive elements in the same process as manufacturing a semiconductor device.

  That is, as shown in FIG. 2C, this assembly 20 is cut along a cutting line 68 between the passive elements 18 by using a dicing machine, and the passive element 10 and the plurality of passive elements are separated. An array 21 having the same is obtained (FIG. 2D).

  Furthermore, the passive element 10, the assembly 20, and the array 21 obtained by such a method can be supplied to a positioning mounting device such as a die bonder or a flip chip die bonder used in a semiconductor package manufacturing process, and thereby the semiconductor package can be supplied. A passive element can be supplied and fixed on a substrate or a semiconductor package substrate mounted on the substrate.

  When attaching and fixing to a semiconductor package, die attach paste and die attach film that are usually used in the semiconductor package manufacturing process can be used, but even if passive elements such as resistors and / or capacitors are fixed with ordinary adhesives Alternatively, it may be fixed with solder without using an adhesive layer.

  In addition, it is preferable to use a dicing die attach film for the passive element of this embodiment because it is not necessary to supply a new adhesive during the positioning mounting. However, when fixing with an adhesive, both paste and film types can be used, and there is a risk of contamination of the substrate and semiconductor chip due to contamination of the adsorbing tool of the positioning and mounting device and bleeding. From the viewpoint of reducing the film thickness, it is desirable to use a film adhesive. Moreover, when mounting on a substrate, various adhesives can be used according to the connection method.

  Further, in this embodiment, a plurality of passive elements such as resistors and / or capacitors may be directly arranged on the adhesive tape (adhesive base material) and supplied to the positioning mounting device. In order to arrange a plurality of resistors and / or capacitors on the tape, it is preferable that passive elements such as resistors and / or capacitors are supplied in the form of intermediate products to be described later.

  Usually, chip resistors or chip capacitors are arranged on the ceramic substrate or silicon substrate by arranging a plurality of the same resistors or capacitors, and after manufacturing a large number of resistors and capacitors at once, they are separated into end terminals. Formed and supplied.

  In the present embodiment, the passive elements can be supplied in the form of an intermediate product (hereinafter referred to as an aggregate) that is an aligned assembly 20 of passive elements such as resistors and capacitors. In this case, the assembly 20 is attached to the adhesive tape 64, attached to the ring-shaped jig 66, and cut into pieces by using a dicing machine used in a normal semiconductor package manufacturing process. In the state where the passive elements such as the resistors and capacitors thus arranged are aligned, the passive element to which the adhesive tape is applied can be obtained. In addition, such a film-like adhesive can be suitably used when a highly thin passive element is used.

  In addition, as described above, the number of resistors or capacitors included in the separated resistors or capacitors may be one or more per piece, and in the case of a plurality, the same type or different types may be used. When a plurality of passive elements such as resistors or capacitors are cut into a single piece, the degree of integration of the passive elements such as resistors or capacitors can be increased.

  On the other hand, when such a construction method is employed, in the multilayer ceramic capacitor, the end face terminal is not formed, and therefore a predetermined capacity cannot be obtained. For this reason, it is necessary to form a through hole during the manufacturing process of the assembly and to connect the internal electrode and the surface electrode.

  As described above, it is preferable that the passive elements disposed in the semiconductor package have a certain thickness. To obtain such thin passive elements such as resistors and capacitors, for example, the assembly 20 In the manufacturing process (see FIG. 2), it is usually necessary to use a thin ceramic substrate or silicon substrate. However, if these substrates are too thin, it becomes difficult to handle the passive elements 10 or the aggregates 20 thereof. As described above, the passive elements are aligned and arranged using a ceramic substrate or silicon substrate thicker than a predetermined thickness. Thereafter, the back surface of the ceramic substrate or silicon substrate may be ground to a predetermined thickness with a grindstone. If an adhesive tape is used to hold the assembly 20 during this grinding process, problems with handling such as damage to the assembly 20 will not occur even if the passive elements are made thinner. Further, the adhesive tape is replaced with the above-mentioned adhesive tape to easily reduce the thickness, and passive elements such as resistors and capacitors arranged on the adhesive tape can be obtained.

(Passive element)
FIG. 3 is a schematic view of the passive element of the present embodiment obtained by dividing the above-described assembly 20 into pieces, and FIG. 4 is a top view of the passive element. In the present embodiment, an example in which a film adhesive is attached to a passive element is shown.

  As shown in FIGS. 3 and 4, the passive element 10 according to the embodiment is formed by attaching a film-like adhesive 16 to the passive element 18 for positioning and fixing in a semiconductor package described later.

  With such a configuration, the film-like adhesive 16 can be cured by high heat treatment performed in the normal process of the passive element 10 to firmly bond the passive element 10, and the semiconductor package of the passive element 10 It can be designed to have high compatibility with the manufacturing process, and is optimized for downsizing and high functionality of electronic devices.

  As the film adhesive 16, a film that exhibits weak adhesiveness in a steady state and cures when heated is preferably used. Specifically, LE-5000 (trade name) manufactured by Lintec Corporation can be used.

  Examples of the passive element 18 include a resistor and a capacitor. The passive element 18 includes an element portion 12 and a terminal 14 provided for wiring. Further, the surface of the terminal 14 may be covered with solder or tin. Thereby, when forming a semiconductor package, the terminal 14 of the passive element 18 can be electrically joined to the substrate constituting the semiconductor package by soldering.

  The surface of the terminal 14 of the passive element 18 may be covered with gold. As a result, when the semiconductor package is formed, the terminals 14 of the passive element 18 can be electrically joined to the substrate constituting the semiconductor package by a technique such as a wire bonding method or a stud bump bonding method.

(Passive elements for semiconductor package manufacturing)
FIG. 5 is a diagram showing an example of a form of a passive element for manufacturing a semiconductor package according to the embodiment of the present invention.
In FIG. 5, the passive elements 10 are aligned on the sheet 22. The sheet 22 is an adhesive base material that holds the film-like adhesive material 16 to hold the passive element 10 for transportation, processing, and the like. Specifically, as described above, a semiconductor device such as a semiconductor package is used. A dicing film and a dicing die attach film used in the manufacturing process can be selected. As a result, a plurality of passive elements 10 are held by the sheet 22 and can be transported and processed at the same time in the form of an assembly 20, and the passive elements 10 can be used as an apparatus used in a semiconductor package manufacturing process. Since it can be applied, the compatibility with this semiconductor package manufacturing process is further increased. The plurality of passive elements 18 may be of the same type or different types.

  Furthermore, the thickness of each passive element 18 such as a resistance element or a capacitor is preferably 50 μm to 150 μm, and more preferably 75 μm to 120 μm. By limiting the thickness of the passive element 18 in this way, it is possible to incorporate passive elements such as resistors and capacitors inside the semiconductor package without increasing the thickness of the semiconductor package.

  Further, when the thickness exceeds 150 μm, the thickness of the semiconductor chip may be exceeded. In this case, the thickness of the semiconductor package is increased. If the thickness is less than 50 μm, the passive element is practically impossible to handle because it is too thin. Therefore, it is preferable to obtain a passive element by a method as described later.

  As described above, the affinity of the passive element with the semiconductor package manufacturing process becomes higher, and the passive element can be handled more easily by reducing the thickness.

(Semiconductor package)
The semiconductor package to which the above-described passive element is applied is such that the above-described passive element is fixed inside via an adhesive tape. Specifically, the semiconductor package is provided on the semiconductor package substrate. The above-mentioned passive element is fixed to the semiconductor package substrate or at least one of the circuit elements through an adhesive tape. When the semiconductor package includes a spacer, the above passive element may be fixed to the spacer via an adhesive tape.

  Here, the semiconductor package substrate refers to a substrate on which each circuit element constituting the semiconductor package and the passive element of the embodiment are mounted. The circuit element refers to an active element and a passive element in addition to a semiconductor element (chip). In the present embodiment, the passive element refers to a passive element to which the above-described film adhesive is attached. The spacer refers to, for example, a silicon spacer that provides a space when stacking circuit elements and passive elements in a semiconductor package, and includes not only a space but also a built-in circuit.

FIG. 6 is a schematic view showing a semiconductor package according to a first application example of the present invention.
In the semiconductor package 26, one passive element 36 and two passive elements 36 are disposed on the back surface at the center of the front surface of the interposer 31 which is the semiconductor package substrate and the solder balls 42 are formed on the back surface. Bonded with a film adhesive.

  A first semiconductor chip 46 and a second semiconductor chip 48, which are two circuit elements, are arranged so as to sandwich the passive element 36 arranged on the surface of the interposer 31, and the interposer is arranged via wires 50 and 51, respectively. 31 is electrically connected.

  Further, a third semiconductor chip 32 as a circuit element electrically connected to the semiconductor chips 46 and 48 is laminated on the first semiconductor chip 46 and the second semiconductor chip 48, and further, a third semiconductor chip 32 is stacked. A fourth semiconductor chip 34 as a circuit element electrically connected to the semiconductor chip 32 is laminated.

  The third semiconductor chip 32 is electrically connected to the interposer 31 via the wire 40. On the other hand, the fourth semiconductor chip 34 is also electrically joined to the interposer 31 via a wire (gold wire) 40. Thus, the third semiconductor chip 32 and the fourth semiconductor chip 34 are electrically connected via the wiring of the interposer 31 and the wires 50 and 51.

  The passive element 36 is joined to the interposer 31 by a conductive paste 44 (or solder or the like), and further, the first to fourth semiconductors are connected to the interposer 31 via wires (not shown), wires 40, 50, 51, and the like. Each of the chips 46, 48, 32, and 34 is electrically joined.

  Further, the semiconductor chip, the passive element, and the like of the semiconductor package 26 are sealed with a resin 38. Further, the resin 38 is filled in a space other than the place where the passive element 36 between the first and second semiconductor chips 46 and 48 is provided.

FIG. 7 is a schematic view showing a semiconductor package according to a second application example of the present invention.
This semiconductor package 28 is the same as that of the first embodiment of the semiconductor package except that the passive element is not embedded on the front and back surfaces of the interposer 31 but is embedded as the passive element 36 on the side surface of the interposer 31. Including the configuration. In addition, the passive element 36 is electrically connected to each of the first to fourth semiconductor chips 46, 48, 32, and 34 via wires (not shown) of the interposer 31 and wires 40, 50, and 51. It has become.

FIG. 8 is a schematic view showing a semiconductor package according to a third application example of the present invention.
This semiconductor package 30 is a semiconductor package except that the passive elements are not the front and back surfaces of the interposer 31 but are arranged as the passive elements 37 on the surface of the third semiconductor chip 32 and are bonded by a film adhesive. The same configuration as that of the first embodiment is included. The passive element 37 is electrically connected to the interposer 31 through wires 41 and 52. Further, the passive element 37 is electrically connected to each of the first to fourth semiconductor chips 46, 48, 32, and 34 via wires (not shown) and wires 40, 50, and 51 of the interposer 31. It has become.

  With such a configuration, it is possible to provide a semiconductor package optimized for downsizing and high functionality of electronic devices.

  Further, the semiconductor package may be formed by arbitrarily combining the first to third application examples. For example, FIG. 9 shows a semiconductor package in which all the embodiments are combined.

  The passive element of the present invention can be applied to a semiconductor package having a structure other than the structure described above, and can also be applied to a normal SMT process.

  Hereinafter, an example of an embodiment of the present invention will be described in detail. In addition, this invention is not limited by this.

One resistor is placed in an area of 0.6mm x 0.3mm by printing a terminal made of a conductive paste at a predetermined position on a 100mm square alumina substrate with a thickness of 200μm and printing a resistance paste. Thus, a resistor assembly was obtained in which the resistor elements were arranged in an array of 200 columns × 110 rows. This resistor assembly was covered with nickel and then gold by plating.
Next, after sticking and holding an adhesive tape on the resistor forming surface of the resistor assembly, the non-resistor forming surface was ground to a thickness of 100 μm with a rotating grindstone.

  Furthermore, the thin resistor element arranged in alignment on the dicing film affixed to the ring by affixing the grounded resistor assembly to the dicing film for semiconductor chip separation and separating each resistor element into individual pieces Got.

  At this time, for the resistor to be mounted on the third semiconductor chip 32, the grinding surface of the resistor assembly is used for the resistor, and for the component to be mounted on the interposer 31, the resistor forming surface of the resistor assembly is used for the dicing film. Affixed to touch.

  The resistor element thus obtained is attached to the multi-die bonder together with the ring and the dicing film, so that the resistor forming surface is interposer on the interposer 31 made of the FR-5 material together with the third semiconductor chip 32. It was mounted with precise alignment so that it was directly opposite. At this time, the semiconductor chip was mounted and fixed on the interposer 31 with an insulating paste adhesive. On the other hand, the resistor retains the resistor by preliminarily printing and applying a conductive paste by screen printing on the land where the resistor terminal on the interposer 31 contacts, and cures the adhesive for mounting the semiconductor. At the same time, the conductive adhesive hardened, and the resistor and the electric circuit on the interposer 31 were electrically connected.

  Some of the resistors were mounted and fixed on the third semiconductor chip 32 with an insulating paste adhesive so that the resistor forming surface was the upper surface. The semiconductor chip thus mounted and the resistor on the semiconductor chip were electrically joined to the electric circuit on the interposer by a gold wire using a wire bonder.

  Next, the semiconductor chip and the resistor mounted and fixed on the interposer were sealed with a sealing resin using a transfer molding machine to complete a semiconductor package. The semiconductor package thus obtained was mounted on a printed wiring board and used for operation confirmation as a semiconductor package, but operated without any problems.

  According to the present invention, a semiconductor package including a resistor / capacitor and a plurality of semiconductor chips can be efficiently manufactured.

An example of the schematic which shows the grinding method of the resistor or capacitor | condenser assembly of this invention is shown. An example of the schematic which shows the supply method of the resistor or capacitor | condenser of this invention is shown. It is the schematic which shows the structure of the passive element which concerns on embodiment of this invention. It is a top view of the said passive element. It is a figure which shows embodiment of the passive element with which the several passive element was arranged in alignment. It is the schematic which shows the semiconductor package which concerns on the 1st application example of this invention. It is the schematic which shows the semiconductor package which concerns on the 2nd application example of this invention. It is the schematic which shows the semiconductor package which concerns on the 3rd application example of this invention. It is the schematic which shows the semiconductor package as a modification of the example of application of this invention.

Explanation of symbols

10 Passive elements (resistors or capacitors separated into individual pieces)
12 Element part 14 Terminal 16 Film adhesive 18 Passive element 19 Board | substrate (resistor or capacitor | condenser aggregate)
20 assembly (ground resistor or capacitor assembly)
21 array (resistor or capacitor array consisting of multiple resistors or capacitors)
26, 28, 30 Semiconductor package 31 Interposer 32 Third semiconductor chip 34 Fourth semiconductor chip 36 Passive element 38 Resin (encapsulant)
40 gold wire
42 Solder balls 44 Conductive paste (or solder)
46 First semiconductor chip 48 Second semiconductor chip 60 Adhesive tape (adhesive tape for holding during grinding)
62 Rotary whetstone 64 Adhesive tape (dicing film)
66 Ring-shaped jig (ring for fixing dicing film)
68 Cutting line

Claims (18)

  A passive element supply method in which an assembly in which passive elements are aligned is thinned, the thinned aggregate is separated into pieces, and the separated passive elements are supplied to a semiconductor package manufacturing apparatus. The method of supplying a passive element according to claim 1,
The method for supplying a passive element is characterized in that the singulation process is an operation of dicing the assembly stuck on the adhesive base material to which the film-like adhesive is stuck to separate it into passive elements. The method of supplying a passive element according to claim 2,
The method for supplying a passive element, wherein the film-like adhesive is attached to the aggregate after the aggregate is thinned. The method of supplying a passive element according to claim 2,
A passive element supply method, wherein the individual passive elements are supplied to a passive element positioning and mounting apparatus in a state in which a film-like adhesive is adhered. The method of supplying a passive element according to claim 1,
The method of supplying a passive element, wherein the thinning process is a grinding process of a back surface of an element forming surface of the passive element. In the supply method of the passive element in any one of Claims 1-5,
A passive element supply method, wherein a terminal surface of the passive element is covered with solder or tin. In the supply method of the passive element in any one of Claims 1-5,
The passive element supply method, wherein the terminal surface of the passive element is covered with gold. In the supply method of the passive element in any one of Claims 1-5,
The passive element supply method, wherein the passive element is a resistor or a capacitor. In the supply method of the passive element in any one of Claims 1-5,
The passive element supply method, wherein the passive element has a thickness of 50 μm or more and 150 μm or less.   A passive element for manufacturing a semiconductor package obtained by thinning an assembly in which passive elements are arranged. The passive element for manufacturing a semiconductor package according to claim 10,
A passive element for manufacturing a semiconductor package, wherein the passive element is affixed on an adhesive substrate to which a film adhesive is affixed. The passive element for manufacturing a semiconductor package according to claim 10 or 11,
A passive element for manufacturing a semiconductor package, wherein the aggregate is composed of the same kind of passive elements. The passive element for manufacturing a semiconductor package according to claim 10 or 11,
The assembly includes a passive element for manufacturing a semiconductor package, wherein the passive element includes different kinds of passive elements. The passive element for manufacturing a semiconductor package according to claim 10 or 11,
A passive element for manufacturing a semiconductor package, wherein a terminal surface of each passive element is covered with solder or tin. The passive element for manufacturing a semiconductor package according to claim 10 or 11,
A passive element for manufacturing a semiconductor package, wherein the surface of each passive element is covered with gold. The passive element for manufacturing a semiconductor package according to claim 10 or 11,
A passive element for manufacturing a semiconductor package, wherein the passive element is a resistor or a capacitor. The passive element for manufacturing a semiconductor package according to claim 10 or 11,
A passive element for manufacturing a semiconductor package, wherein the thickness of each passive element is 50 μm or more and 150 μm or less. A passive element obtained by singulating a passive element for manufacturing a semiconductor package according to claim 10.

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