JP2005116566A - Adhesive for fixing semiconductor element, method of supplying adhesive to semiconductor element, semiconductor device and its manufacturing method - Google Patents
Adhesive for fixing semiconductor element, method of supplying adhesive to semiconductor element, semiconductor device and its manufacturing method Download PDFInfo
- Publication number
- JP2005116566A JP2005116566A JP2003344903A JP2003344903A JP2005116566A JP 2005116566 A JP2005116566 A JP 2005116566A JP 2003344903 A JP2003344903 A JP 2003344903A JP 2003344903 A JP2003344903 A JP 2003344903A JP 2005116566 A JP2005116566 A JP 2005116566A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- adhesive
- fixing
- semiconductor
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
本発明は、複数の半導体素子をひとつのパッケージに搭載した半導体装置に関するものであり、特に、小型・軽量化及び高機能・大容量化を目的とする半導体素子の3次元積層技術に係わるものである。 The present invention relates to a semiconductor device in which a plurality of semiconductor elements are mounted in one package, and more particularly to a three-dimensional stacking technique of semiconductor elements for the purpose of miniaturization, weight reduction, high function, and large capacity. is there.
近年の電子機器の高機能化並びに軽薄短小化の要求に伴い、電子部品の高密度集積化、さらには高密度実装化が進んできている。これらの電子機器に使用される半導体パッケージは、小型化かつ多ピン化してきており、従来のように金属製リードフレームに半導体素子を一つずつ搭載し、金線により電気的接続をとる方法では十分なリード間隔を確保できずに半導体素子の小型化を阻害していた。 With recent demands for higher functionality and lighter, thinner and smaller electronic devices, electronic components have been increasingly integrated and densely packaged. Semiconductor packages used in these electronic devices have become smaller and have more pins, and in the conventional method of mounting semiconductor elements one by one on a metal lead frame and electrically connecting them with gold wires, A sufficient lead interval could not be ensured, which hindered downsizing of the semiconductor element.
従来のようなリードフレームを使用した形態のパッケージでは、小型化に限界がきているため、最近では回路基板上にチップを実装したものとして、BGA(Ball Grid Array)や、CSP(Chip Scale Package)と言った、エリア実装型の新しいパッケージ方式が提案されている。これらの半導体パッケージにおいて、半導体素子の電極と従来型半導体パッケージのリードフレームの機能を有する、半導体パッケージ用基板と呼ばれる、プラスチックやセラミックス等各種材料を使って構成される、サブストレートの端子との電気的接続方法として、ワイヤーボンディング方式やTAB(Tape Automated Bonding)方式、さらにはFC(Frip Chip)方式などが知られているが、最近では、半導体パッケージの小型化に有利なFC接続方式を用いた、BGAやCSPの構造が盛んに提案されている。 In conventional packages using a lead frame, there is a limit to miniaturization, and recently, it is assumed that a chip is mounted on a circuit board, and BGA (Ball Grid Array) or CSP (Chip Scale Package). A new area-mounting package system has been proposed. In these semiconductor packages, the electrical connection between the electrodes of the semiconductor element and the terminals of the substrate, which is made of various materials such as plastics and ceramics, called the semiconductor package substrate, has the function of the lead frame of the conventional semiconductor package. As a general connection method, a wire bonding method, a TAB (Tape Automated Bonding) method, and an FC (Flip Chip) method are known, but recently, an FC connection method advantageous for miniaturization of a semiconductor package has been used. BGA and CSP structures have been actively proposed.
更に実装密度を向上させるために、一つの半導体パッケージの内部に複数個の半導体素子を積み重ねて収納することにより、実装密度を向上させる手法が提案されている。(例えば、特許文献1参照)しかしながら、これらの用途に用いられる半導体素子固定用接着剤は、その被着面がリードフレームと異なり平坦でないため接着剤内部若しくは被着物との界面にボイドが残留しやすいと言う問題を抱えていた。 In order to further improve the mounting density, a technique for improving the mounting density by stacking and storing a plurality of semiconductor elements in one semiconductor package has been proposed. (For example, refer to Patent Document 1) However, the adhesive for fixing a semiconductor element used in these applications is not flat unlike the lead frame, and therefore voids remain inside the adhesive or at the interface with the adherend. I had the problem of being easy.
本発明は、従来のこのような問題点を解決するためになされたもので、その目的とするところは、平坦でない被着面に半導体素子を接着剤を用いて固定する際のボイドの残留を低減させることが可能な半導体素子の製造方法を提供することにある。 The present invention has been made to solve the above-described conventional problems, and the object of the present invention is to prevent residual voids when a semiconductor element is fixed to a non-flat adherend using an adhesive. An object of the present invention is to provide a method of manufacturing a semiconductor device that can be reduced.
発明者らは種々検討の結果、半導体素子の裏面にあらかじめ接着剤が供給されており、該半導体素子をマウントする際に半導体素子中央部の接着剤が半導体素子周辺の接着剤厚みより厚くなっており且つ該接着剤としてマウント時の温度で流動可能な粘度である接着剤を選択することによりボイド残留のない半導体素子の製造が可能となることを見出したものである。 As a result of various studies, the inventors have previously supplied an adhesive to the back surface of the semiconductor element, and when mounting the semiconductor element, the adhesive at the center of the semiconductor element is thicker than the adhesive thickness around the semiconductor element. In addition, it has been found that by selecting an adhesive having a viscosity capable of flowing at the temperature at the time of mounting as the adhesive, it is possible to manufacture a semiconductor element free from voids.
即ち本発明は、
[1] 半導体素子を固定する際に予め半導体素子裏面に供給されている半導体素子固定用接着剤であって、接着剤を付与された半導体素子が被着物に接する際にその厚みが半導体素子端部から500μmの幅の厚みの平均値(以後周辺部の厚みと呼称)より中央部500μm四方の部位の平均厚み(以後中央部厚みと呼称)が15%以上厚くなっていることを特徴とする半導体素子固定用接着剤、
[2] 半導体素子が被着物に接する際の温度の溶融粘度が50Pa・s以下である[1]項記載の半導体素子固定用接着剤、
[3] 接着剤が、室温では固体であり、加熱されることにより溶融しその表面張力により半導体素子中央部分の接着剤厚みが周辺部厚みよりも厚くなるものである[1]又は[2]項記載の半導体素子固定用接着剤、
[4] [1]〜[3]項のいずれかに記載された半導体固定用接着剤を半導体素子裏面に、スクリーン印刷又はステンシル印刷の方法で半導体素子中央部の接着剤厚みが周辺部分の厚みよりも厚くなるように配置することを特徴とする半導体素子への接着剤の供給方法、
[5] [1]〜[3]項のいずれかに記載された半導体素子固定用接着剤と[4]項記載の半導体素子への接着材の供給方法を用いて製造されたことを特徴とする半導体装置、
[6] [1]〜[3]項のいずれかに記載された半導体素子固定用接着剤と[4]項記載の半導体素子への接着材の供給方法を用いて製造することを特徴とする半導体装置の製造方法
である。
That is, the present invention
[1] An adhesive for fixing a semiconductor element, which is supplied to the back surface of the semiconductor element in advance when fixing the semiconductor element, and the thickness of the adhesive when the semiconductor element to which the adhesive is applied contacts the adherend The average thickness (hereinafter referred to as the central portion thickness) of the central portion of 500 μm is 15% or more thicker than the average thickness (hereinafter referred to as the peripheral portion thickness) having a width of 500 μm from the portion. Semiconductor element fixing adhesive,
[2] The adhesive for fixing a semiconductor element according to [1], wherein the melt viscosity at a temperature when the semiconductor element contacts the adherend is 50 Pa · s or less,
[3] The adhesive is solid at room temperature, melts when heated, and the surface tension causes the adhesive thickness at the central portion of the semiconductor element to be thicker than the peripheral thickness [1] or [2] The adhesive for fixing a semiconductor element according to item,
[4] The adhesive for semiconductor fixing described in any one of [1] to [3] is applied to the back surface of the semiconductor element, and the thickness of the adhesive at the central part of the semiconductor element is the thickness of the peripheral part by screen printing or stencil printing. A method of supplying an adhesive to a semiconductor element, characterized by being arranged to be thicker than
[5] A semiconductor element fixing adhesive described in any one of [1] to [3] and a method for supplying an adhesive to a semiconductor element described in [4]. Semiconductor device,
[6] A semiconductor element fixing adhesive described in any one of [1] to [3] and a method for supplying an adhesive to a semiconductor element described in [4]. A method for manufacturing a semiconductor device.
本発明によれば、半導体素子裏面に接着剤を付与し、半導体素子を加熱し接着剤層が溶融し接着剤層の中央部分が周辺部分よりも厚くした状態で積層することで、平坦でない被着面にボイド残留なく半導体素子を固定することを可能にするものである。 According to the present invention, the adhesive is applied to the back surface of the semiconductor element, the semiconductor element is heated, the adhesive layer is melted, and the central portion of the adhesive layer is laminated so as to be thicker than the peripheral portion. This makes it possible to fix the semiconductor element without any voids remaining on the contact surface.
本発明は、まず半導体素子の裏に接着剤を配置するが供給の方法としては、ウェハーの状態でスピンコート、印刷、ドライフィルム化してのラミネーションの方法を取ることが出来る。 このようにして得られた接着剤つき半導体ウェハーはダイシングマシンにより個片化され、ダイボンディングに供せられる。 In the present invention, an adhesive is first arranged on the back of a semiconductor element. As a supply method, a method of lamination by spin coating, printing or dry film formation in a wafer state can be employed. The thus obtained semiconductor wafer with an adhesive is separated into pieces by a dicing machine and used for die bonding.
ダイボンディングの工程においては、半導体素子裏面に供給された接着剤が被着面中央から周辺部に向かって濡れていくようにするため、半導体素子に供給された接着剤が半導体素子周辺部より中央部の方が厚くなった状態であることが必要である。このためには加熱により溶融する接着剤を選択し、ダイシングフィルムからピックアップし位置合わせする間に半導体素子をピックアップツール側から加熱することによりこの形状を実現する。具体的にはボンディング温度での接着剤の溶融粘度が50Pa・s以下であることが必要であり、好ましくは3Pa・sから0.1Pa・sであることが望ましい。上限値以上では樹脂の流動が十分でなくボイドの残留を抑制することが出来ないため好ましくない。 In the die bonding process, the adhesive supplied to the back surface of the semiconductor element is wetted from the center of the adherend surface toward the peripheral portion. The part needs to be thicker. For this purpose, an adhesive that melts by heating is selected, and this shape is realized by heating the semiconductor element from the pickup tool side while picking up and aligning from the dicing film. Specifically, the melt viscosity of the adhesive at the bonding temperature is required to be 50 Pa · s or less, preferably 3 Pa · s to 0.1 Pa · s. Above the upper limit, the flow of the resin is not sufficient and residual voids cannot be suppressed.
また、供給する接着剤量によってはピックアップツールからの加熱だけでは周辺部と中央部の厚みの差が十分に得られない場合があるが、この場合は半導体素子の接着剤供給面中央部に追加の接着剤をスクリーン印刷若しくはステンシル印刷で供給することが好ましい。
この結果得られる、ダイボンディング時の接着剤の厚みは中央部が周辺部より15%以上厚くなっている必要があり、好ましくは18%以上30%未満であることが望ましい。
下限値未満では、被着面の平坦度によっては、被着面端部に接着剤が先に接触し、ボイドの抜けを阻害してしまう。
Also, depending on the amount of adhesive to be supplied, there may be cases where a sufficient difference in thickness between the peripheral part and the central part cannot be obtained only by heating from the pick-up tool. The adhesive is preferably supplied by screen printing or stencil printing.
As a result, the thickness of the adhesive obtained at the time of die bonding needs to be 15% or more thicker at the center part than the peripheral part, and preferably 18% or more and less than 30%.
If it is less than the lower limit, depending on the flatness of the adherend surface, the adhesive first comes into contact with the end portion of the adherend surface, thereby preventing the void from being removed.
上記の発明を用いて、半導体素子をマウントすれば被着面の凹凸に関係なくボイドなく半導体素子を固定することが出来る。 If the semiconductor element is mounted using the above invention, the semiconductor element can be fixed without voids regardless of the unevenness of the deposition surface.
以下に、本発明の実施形態の一例を詳細に説明する。なお、本発明は、これにより限定されるものではない。 Hereinafter, an example of an embodiment of the present invention will be described in detail. In addition, this invention is not limited by this.
まず、厚さ200μmの半導体ウェハー機能面裏面全面にステンシル印刷により、液状接着剤(住友ベークライト製 CRP−X4291)を配置した。この後、123℃で1時間乾燥することにより、接着剤をBステージ化させた。この際の接着剤厚みは中央部周辺部に差がなく、147μmであった。 First, a liquid adhesive (CRP-X4291 manufactured by Sumitomo Bakelite Co., Ltd.) was placed on the entire back surface of the functional surface of a semiconductor wafer having a thickness of 200 μm by stencil printing. Thereafter, the adhesive was B-staged by drying at 123 ° C. for 1 hour. At this time, the thickness of the adhesive was 147 μm with no difference in the peripheral part of the central part.
次に、接着剤面にロールラミネーターによりダイシングフィルム(リンテック■製 D
−510T)を貼り付けた。
Next, a dicing film (Lintec D
-510T).
この後、ダイシングマシンにより半導体素子を個片化することにより、裏面に接着剤が供給された積層素子を得た。 Thereafter, the semiconductor element was separated into pieces by a dicing machine to obtain a laminated element having an adhesive supplied to the back surface.
次に入出力端子が半導体素子中心線上に配置され、積層素子と同サイズのセンターパッド素子を有機サブストレート上にダイアタッチペーストを用いて搭載し、半導体素子と有機サブストレートを、金線により接続した。 この際の最高ワイヤー高さは138μmであった。 Next, input / output terminals are arranged on the center line of the semiconductor element, and a center pad element of the same size as the laminated element is mounted on the organic substrate using a die attach paste, and the semiconductor element and the organic substrate are connected by a gold wire. did. The maximum wire height at this time was 138 μm.
次に積層素子を150℃に加熱しながら荷重0.005Nで、センターパッド素子上に積層した。この際の接着剤の溶融粘度は0.36Pa・sであり、接着剤の周辺部の厚みは132.9μm中央部の厚みは157.3μmであった。このようにして得られたセンターパッド素子上に積層素子が積層された構造物はX線観察により金線同士の接触がないことが確認された。また、断面を削りだして確認することにより積層素子、センターパッド素子のどちらにも接触していないことが確認された。加えて、素子端部からの樹脂染み出しも少なく、積層素子表面への回り込み及びワイヤーボンディングパッドの汚染も確認されなかった。 Next, the laminated element was laminated on the center pad element with a load of 0.005 N while being heated to 150 ° C. The melt viscosity of the adhesive at this time was 0.36 Pa · s, and the thickness of the peripheral part of the adhesive was 132.9 μm, and the thickness of the central part was 157.3 μm. It was confirmed by X-ray observation that the structure in which the laminated elements were laminated on the center pad element thus obtained had no contact between the gold wires. Further, it was confirmed that neither the laminated element nor the center pad element was in contact by cutting and checking the cross section. In addition, resin seepage from the end of the element was small, and no wraparound to the surface of the laminated element and contamination of the wire bonding pad were confirmed.
このようにして得られた構造物は、積層素子が金線により有機サブストレートと電気的に接続され、封止樹脂(住友ベークライト製EME−G770)によって封止された。 このようにして得られた半導体装置は、半導体としての動作確認を行ない、半導体素子としての動作に何の問題のないことが確認された。 In the structure thus obtained, the laminated element was electrically connected to the organic substrate by a gold wire, and sealed with a sealing resin (EME-G770 manufactured by Sumitomo Bakelite). The semiconductor device thus obtained was checked for operation as a semiconductor, and it was confirmed that there was no problem in operation as a semiconductor element.
本発明は、表面が平坦でない被着面に半導体素子を搭載する際に接着剤中のボイドを抑制することが出来る半導体装置の製造方法であり、特に被着面としてバンプ若しくはワイヤーが存在半導体素子上に更に半導体素子を積層して搭載する場合に半導体装置に好適に用いることができる。 The present invention relates to a method of manufacturing a semiconductor device capable of suppressing voids in an adhesive when a semiconductor element is mounted on an adherend surface having a non-flat surface, and in particular, a bump or wire exists as the adherend surface. When a semiconductor element is further stacked and mounted thereon, it can be suitably used for a semiconductor device.
1 第1の半導体素子
2 半導体素子固定用接着剤
3 第2の半導体素子
4 金線
5 半導体素子固定用接着剤
6 封止樹脂
7 有機サブストレート
DESCRIPTION OF SYMBOLS 1
Claims (6)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003344903A JP2005116566A (en) | 2003-10-02 | 2003-10-02 | Adhesive for fixing semiconductor element, method of supplying adhesive to semiconductor element, semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003344903A JP2005116566A (en) | 2003-10-02 | 2003-10-02 | Adhesive for fixing semiconductor element, method of supplying adhesive to semiconductor element, semiconductor device and its manufacturing method |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005116566A true JP2005116566A (en) | 2005-04-28 |
Family
ID=34538377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003344903A Pending JP2005116566A (en) | 2003-10-02 | 2003-10-02 | Adhesive for fixing semiconductor element, method of supplying adhesive to semiconductor element, semiconductor device and its manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2005116566A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007157758A (en) * | 2005-11-30 | 2007-06-21 | Sumitomo Bakelite Co Ltd | Adhesive film for semiconductor and semiconductor device using the same |
JP2012028443A (en) * | 2010-07-21 | 2012-02-09 | Denso Corp | Semiconductor device and method of manufacturing the same |
WO2012073972A1 (en) * | 2010-12-01 | 2012-06-07 | 日立化成工業株式会社 | Semiconductor wafer with adhesive layer, method for manufacturing semiconductor device, and semiconductor device |
-
2003
- 2003-10-02 JP JP2003344903A patent/JP2005116566A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007157758A (en) * | 2005-11-30 | 2007-06-21 | Sumitomo Bakelite Co Ltd | Adhesive film for semiconductor and semiconductor device using the same |
JP2012028443A (en) * | 2010-07-21 | 2012-02-09 | Denso Corp | Semiconductor device and method of manufacturing the same |
WO2012073972A1 (en) * | 2010-12-01 | 2012-06-07 | 日立化成工業株式会社 | Semiconductor wafer with adhesive layer, method for manufacturing semiconductor device, and semiconductor device |
CN103250235A (en) * | 2010-12-01 | 2013-08-14 | 日立化成株式会社 | Semiconductor wafer with adhesive layer, method for manufacturing semiconductor device, and semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6897552B2 (en) | Semiconductor device wherein chips are stacked to have a fine pitch structure | |
JP4998268B2 (en) | Semiconductor device and manufacturing method thereof | |
US7242081B1 (en) | Stacked package structure | |
JP5227501B2 (en) | Stack die package and method of manufacturing the same | |
US7679178B2 (en) | Semiconductor package on which a semiconductor device can be stacked and fabrication method thereof | |
US20090134507A1 (en) | Adhesive on wire stacked semiconductor package | |
KR20080020069A (en) | Semiconductor package and method for fabricating the same | |
US20080138934A1 (en) | Method of manufacturing multi-stack package | |
US20050285250A1 (en) | Stacked multi-chip semiconductor package improving connection reliability of stacked chips | |
US20060076665A1 (en) | Package stack and manufacturing method thereof | |
WO2003098687A1 (en) | Semiconductor device and its manufacturing method | |
JP2001223326A (en) | Semiconductor device | |
US20040227223A1 (en) | Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing semiconductor device and electronic device | |
JP4175138B2 (en) | Semiconductor device | |
US20100032831A1 (en) | Bump structure foe semiconductor device | |
JP2007242684A (en) | Laminated semiconductor device and laminating method of device | |
JP4626445B2 (en) | Manufacturing method of semiconductor package | |
US8035220B2 (en) | Semiconductor packaging device | |
JP2005116566A (en) | Adhesive for fixing semiconductor element, method of supplying adhesive to semiconductor element, semiconductor device and its manufacturing method | |
JP2008277457A (en) | Multilayer semiconductor device and package | |
KR100650728B1 (en) | stacked package and method for manufacturing the same | |
JP2007116030A (en) | Semiconductor device and semiconductor package using it | |
US8975758B2 (en) | Semiconductor package having interposer with openings containing conductive layer | |
JP4473668B2 (en) | Semiconductor device and manufacturing method thereof | |
JP4439339B2 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060606 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20080630 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080722 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080922 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081021 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081222 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090127 |