JP3756818B2 - メモリ制御回路および制御システム - Google Patents

メモリ制御回路および制御システム Download PDF

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Publication number
JP3756818B2
JP3756818B2 JP2002002184A JP2002002184A JP3756818B2 JP 3756818 B2 JP3756818 B2 JP 3756818B2 JP 2002002184 A JP2002002184 A JP 2002002184A JP 2002002184 A JP2002002184 A JP 2002002184A JP 3756818 B2 JP3756818 B2 JP 3756818B2
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Japan
Prior art keywords
memory
signal
voltage
data
controller
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JP2002002184A
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Japanese (ja)
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JP2003203044A5 (enExample
JP2003203044A (ja
Inventor
元 佐々木
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MegaChips Corp
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MegaChips Corp
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Priority to JP2002002184A priority Critical patent/JP3756818B2/ja
Priority to US10/334,893 priority patent/US6721212B2/en
Publication of JP2003203044A publication Critical patent/JP2003203044A/ja
Publication of JP2003203044A5 publication Critical patent/JP2003203044A5/ja
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Publication of JP3756818B2 publication Critical patent/JP3756818B2/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
JP2002002184A 2002-01-09 2002-01-09 メモリ制御回路および制御システム Expired - Fee Related JP3756818B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2002002184A JP3756818B2 (ja) 2002-01-09 2002-01-09 メモリ制御回路および制御システム
US10/334,893 US6721212B2 (en) 2002-01-09 2003-01-02 Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002002184A JP3756818B2 (ja) 2002-01-09 2002-01-09 メモリ制御回路および制御システム

Publications (3)

Publication Number Publication Date
JP2003203044A JP2003203044A (ja) 2003-07-18
JP2003203044A5 JP2003203044A5 (enExample) 2004-09-02
JP3756818B2 true JP3756818B2 (ja) 2006-03-15

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002002184A Expired - Fee Related JP3756818B2 (ja) 2002-01-09 2002-01-09 メモリ制御回路および制御システム

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US (1) US6721212B2 (enExample)
JP (1) JP3756818B2 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
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US7301961B1 (en) 2001-12-27 2007-11-27 Cypress Semiconductor Corportion Method and apparatus for configuring signal lines according to idle codes
US6879523B1 (en) * 2001-12-27 2005-04-12 Cypress Semiconductor Corporation Random access memory (RAM) method of operation and device for search engine systems
JP3963744B2 (ja) * 2002-03-15 2007-08-22 富士通株式会社 チップセレクト信号による制御を変更可能なメモリ装置
US20050086423A1 (en) * 2003-10-17 2005-04-21 Zitlaw Clifford A. System and method for implementing a NAND memory interface
KR100596776B1 (ko) * 2004-01-08 2006-07-04 주식회사 하이닉스반도체 멀티 칩 어셈블리 및 이의 구동 방법
FR2888032A1 (fr) * 2005-06-30 2007-01-05 Gemplus Sa Procede de gestion de memoire non volatile dans une carte a puce
US7554843B1 (en) * 2005-11-04 2009-06-30 Alta Analog, Inc. Serial bus incorporating high voltage programming signals
JP2007172333A (ja) * 2005-12-22 2007-07-05 Sanyo Electric Co Ltd バスアドレス選択回路およびバスアドレス選択方法
JP2007172332A (ja) * 2005-12-22 2007-07-05 Sanyo Electric Co Ltd メモリ制御回路及びメモリ制御方法
KR100663384B1 (ko) * 2005-12-30 2007-01-02 엠텍비젼 주식회사 메모리 인터페이스 장치 및 방법
US7451263B2 (en) * 2006-02-08 2008-11-11 Infineon Technologies Ag Shared interface for components in an embedded system
US7978541B2 (en) * 2007-01-02 2011-07-12 Marvell World Trade Ltd. High speed interface for multi-level memory
US8874831B2 (en) 2007-06-01 2014-10-28 Netlist, Inc. Flash-DRAM hybrid memory module
US7688628B2 (en) * 2007-06-30 2010-03-30 Intel Corporation Device selection circuit and method
JP2009048409A (ja) 2007-08-20 2009-03-05 Canon Inc インターフェース回路及び該回路を備えた集積回路装置
JP2010252090A (ja) * 2009-04-16 2010-11-04 Rohm Co Ltd 半導体装置
US9342445B2 (en) 2009-07-23 2016-05-17 Hgst Technologies Santa Ana, Inc. System and method for performing a direct memory access at a predetermined address in a flash storage
JP2012048427A (ja) * 2010-08-25 2012-03-08 Sony Corp 情報処理装置、情報処理方法及びプログラム
WO2012064670A1 (en) * 2010-11-09 2012-05-18 Rambus Inc. Area-efficient multi-modal signaling interface
JP5839474B2 (ja) * 2011-03-24 2016-01-06 株式会社半導体エネルギー研究所 信号処理回路
CN104303167B (zh) 2012-05-08 2018-01-23 马维尔国际贸易有限公司 计算机系统和存储器管理的方法
JP6030951B2 (ja) * 2012-12-28 2016-11-24 ルネサスエレクトロニクス株式会社 半導体装置及び電子装置
US9081666B2 (en) 2013-02-15 2015-07-14 Seagate Technology Llc Non-volatile memory channel control using a general purpose programmable processor in combination with a low level programmable sequencer
US9088445B2 (en) * 2013-03-07 2015-07-21 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
WO2015116128A1 (en) * 2014-01-31 2015-08-06 Hewlett-Packard Development Company, L.P. Signal return path
JP6230588B2 (ja) * 2015-12-25 2017-11-15 ルネサスエレクトロニクス株式会社 半導体装置
CN112559411B (zh) * 2020-12-24 2023-03-31 西安翔腾微电子科技有限公司 一种基于ttl与lvttl接口的转换电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6161162A (en) * 1993-12-08 2000-12-12 Nec Corporation Multiprocessor system for enabling shared access to a memory
US20030009616A1 (en) * 1994-11-30 2003-01-09 Brian K. Langendorf Method and apparatus for integrating and determining whether a memory subsystem is installed with standard page mode memory or an extended data out memory
US5687382A (en) * 1995-06-07 1997-11-11 Hitachi America, Ltd. High speed, reduced power memory system implemented according to access frequency
US6247084B1 (en) * 1997-10-08 2001-06-12 Lsi Logic Corporation Integrated circuit with unified memory system and dual bus architecture
JP3856928B2 (ja) 1997-11-18 2006-12-13 松下電器産業株式会社 特定用途向け集積回路及び電子装置
JP2000010683A (ja) 1998-06-26 2000-01-14 Hitachi Ltd 双方向電圧変換回路および情報処理装置
JP2000105644A (ja) 1998-09-29 2000-04-11 Ricoh Co Ltd バス制御装置
KR100291897B1 (ko) * 1999-03-11 2001-06-01 윤종용 버스트 모드 액세스를 구비한 반도체 메모리 장치
KR100368133B1 (ko) * 2000-03-28 2003-01-15 한국과학기술원 메모리 셀 정보 저장 방법

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Publication number Publication date
US6721212B2 (en) 2004-04-13
US20030137881A1 (en) 2003-07-24
JP2003203044A (ja) 2003-07-18

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