US6721212B2 - Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces - Google Patents

Memory control circuit and control system for a plurality of memories interconnected via plural logic interfaces Download PDF

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US6721212B2
US6721212B2 US10/334,893 US33489303A US6721212B2 US 6721212 B2 US6721212 B2 US 6721212B2 US 33489303 A US33489303 A US 33489303A US 6721212 B2 US6721212 B2 US 6721212B2
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memory
signal
data
voltage
controller
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US20030137881A1 (en
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Gen Sasaki
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MegaChips Corp
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MegaChips Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1684—Details of memory controller using multiple buses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a memory control circuit for controlling a plurality of memories corresponding to a plurality of logic interfaces, respectively.
  • a controller incorporating a CPU usually requires two kinds of memories: nonvolatile memories such as a ROM (Read Only Memory) for storing an activation program, initial data and the like and a flash memory (hereinafter, referred to as “boot memory”), and volatile RAMs (Random Access Memory) used for storage of loaded programs and temporary storage of variables.
  • nonvolatile memories such as a ROM (Read Only Memory) for storing an activation program, initial data and the like and a flash memory (hereinafter, referred to as “boot memory”)
  • volatile RAMs Random Access Memory
  • the controller and these memories are interconnected via a bus, and as a logic interface standard for connecting these controller and memories, TTL (Transistor—Transistor Logic) and LVTTL (Low-Voltage TTL), SSTL (Stub Series Terminated Logic), LS-TTL (Low power Schottky-TTL) and the like are employed.
  • Each memory has an input/output interface (level shifter) for converting an input voltage into an internal voltage and converting the internal voltage into an output voltage according to the logic interface.
  • input voltages that are determined as “high level” (V IH ) are defined in the range of 2 V (volts) to V DD +0.3 V (volts)
  • input voltages that are determined as “low level” (V IL ) are defined in the range of ⁇ 0.3 V (volts) to +0.8 V (volts)
  • values in the vicinity of 3.3 V are recommended as the value of the source voltage V DD .
  • the minimum value of high level output voltages (V OH ) is defined as 2.4 V
  • the maximum value of low level output voltages (V OH ) is defined as 0.4 V.
  • a bus can be shared for transmitting address signals, control signals and data signals without any problems.
  • a bus is shared in the condition that these memories use different logic interfaces and thus the source voltages V DD are different, a voltage higher than the input withstand pressure is applied to a memory supporting lower source voltage, causing a latch-up and the like, which triggers a breakdown in the input/output interface, instability of operation of the memory and the like problems.
  • the bus wiring can be arranged individually and separately for each of the memories using different source voltages V DD .
  • FIG. 13 is a schematic view showing one example of a memory control circuit adopting separate bus wiring for individual memories.
  • This memory control circuit includes a controller 100 1 incorporating a CPU 101 , a boot memory 115 implemented by a nonvolatile memory, and a RAM 114 .
  • the source voltage V DD of the RAM 114 is 2.5 V
  • the source voltage V DD of the boot memory 115 is 3.3 V
  • these memories adopt different source voltages.
  • a first control bus 110 for transmitting address signals and control signals to the RAM 114 and a first data bus 111 for transmitting data signals are disposed, and between the controller 100 1 and the boot memory 115 a second control bus 112 which is separate from the control bus 110 and a second data bus 113 which is separate from the data bus 111 are disposed.
  • controller 100 is equipped with a PAD circuit 105 supporting a logic interface of the RAM 114 and a PAD circuit 106 supporting a logic interface of the nonvolatile memory 115 .
  • the PAD circuit 105 supporting the low voltage standard of the RAM 114 has two level converters 105 A and 105 B for converting voltage level of input signal.
  • the level converter 105 A converts the voltage levels of an address signal AD in and a control signal CT in inputted from the memory controller 103 and outputs signals after conversion to the control bus 110 via an output port 107 A for supplying to the RAM 114 .
  • write data DO output from the CPU 101 is converted into data RD at the level converter 105 B and transferred via the data bus 111 from an input/output port 107 B to the RAM 114 to be written therein.
  • a data signal read from the RAM 114 is transferred via the data bus 111 to be inputted to the input/output port 107 B, and converted at the level converter 105 B into data RD in and inputted to the “1” side terminal of the selector 104 .
  • the memory controller 103 supplies the selector 104 with a selection signal of high level.
  • the selector 104 selects the data RD in and outputs it as readout data DI to the CPU 101 .
  • the PAD circuit 106 which supports the high voltage standard of the nonvolatile memory 115 has two level converters 106 A and 106 B.
  • the level converter 106 A converts the voltage levels of an address signal AD in and a control signal CT in inputted from the memory controller 103 and outputs signals after conversion to the control bus 112 via an output port 107 C for supplying to the nonvolatile memory 115 .
  • a data signal read out from the nonvolatile memory 115 is transferred to an input port 107 D via the data bus 113 and converted to data NVD in at the level converter 106 B to be inputted to the “0” side terminal of the selector 104 .
  • the selector 104 selects data NVD in in response to that selection signal, and outputs it to the CPU 101 as readout data DI.
  • a control bus 120 and a data bus 121 are shared by the RAM 114 (source voltage 2.5 V standard) and the nonvolatile memory 115 (source voltage 3.3 V standard).
  • a data signal outputted from the nonvolatile memory 115 is converted into a signal conforming to the low voltage standard for the RAM 114 at a level converter 123 and then outputted to the data bus 121 .
  • the controller 100 2 described above includes a PAD circuit 105 conforming to the low voltage standard of the RAM 114 , a CPU 101 and a memory interface 102 .
  • the CPU 101 first issues an access request with respect to the MIU 102 .
  • the MIU 102 fetches an address signal AD 0 and a control signal CT 0 transferred from the CPU 101 and outputs them as an address signal AD in and a control signal CT in in predetermined timing.
  • the level converter 105 A converts the voltage levels of the input signals AD in and CT in and outputs signals after conversion to the control bus 120 via the output port 107 A for supplying to the memories 114 and 115 .
  • the level converter 105 B converts the level of the data DO transferred from the CPU 101 and outputs a signal after conversion to the data bus 121 via the input/output port 107 B for supplying to the RAM 114 .
  • a data signal MD read out from the RAM 114 is transferred to the input port 107 B via the data bus 121 , converted to readout data DI at the level converter 105 B and then inputted to the CPU 101 .
  • a memory control circuit controls a plurality of memories having logic interfaces corresponding to different source voltages from each other, which includes a control bus, a first data bus, a second data bus and a controller.
  • the control bus includes signal lines for transmitting an address signal and a control signal to and from a low voltage memory which operates at the minimum source voltage among the plurality of memories.
  • the first data bus includes signal lines for transmitting data signals to and from the low voltage memory.
  • the second data bus includes signal lines for transmitting data signals to and from a high voltage memory operating at a source voltage higher than the source voltage of the low voltage memory among the plurality of memories, and disposed independently from the first data bus.
  • the controller accesses the low voltage memory and the high voltage memory via the control bus, first data bus and second data bus.
  • the control bus has signal lines which branch off the signal lines of the control bus to be connected to the high voltage memory and transmit an address signal and a control signal to the high voltage memory.
  • an address signal and a control signal supplied to the low voltage memory and the high voltage memory are transmitted via the common control bus. Therefore, the number of signal lines of the control bus can be reduced, and the number of pins for data input/output at the controller can be reduced. In addition, since the number of signal lines of the control bus is small, power consumption at the memory control circuit can be reduced. Furthermore, since the address signal and the control signal are transmitted at a voltage level in conformance with the logic interface of low voltage level, a voltage exceeding the acceptable level will not be applied to the low voltage memory, resulting that both the low voltage memory and the high voltage memory can be operated in a stable manner.
  • the controller includes first to third level converters.
  • the first level converter outputs the address signal and the control signal obtained by converting voltage levels of internal signals in accordance with the input voltage defined by the logic interface of the low voltage memory to the control bus.
  • the second level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the low voltage memory, and sends/receives the data signal via the first data bus.
  • the third level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the high voltage memory, and sends/receives the data signal via the second data bus.
  • the range of output voltages defined by the logic interface of the low voltage memory is included in a range of input voltages defined by the logic interface of the high voltage memory.
  • a RAM random access memory
  • a nonvolatile memory is used as the high voltage memory.
  • the first data bus branches off to be connected to the high voltage memory for transmitting either one or both of the address signal and the control signal to the high voltage memory.
  • a memory control circuit includes a controller which accesses one of a first memory group and a second memory group.
  • the first memory group includes a plurality of memories having logic interfaces corresponding to different source voltages from each other
  • the second memory group includes a plurality of memories having logic interfaces corresponding to the same source voltage as each other.
  • the memory control circuit according to the sixth aspect of the present invention is provided with a memory control circuit according to any of the first to fifth aspects when the controller accesses the first memory group.
  • the control bus and the first data bus in the memory control circuit according to any of the first to fifth aspects of the present invention are shared and connected with all the memories of the second memory group, and the second data bus in the memory control circuit according to any of the first to fifth aspects of the present invention is used for signal transmission other than the sending/receiving of control signal and data signal to/from the memories.
  • the controller when the controller accesses the second memory group, the controller can use the second data bus and the third level converter usable in accessing to the first memory group, for signal transmission other than sending/receiving of control signal and data signal to/from the memories, so that a general-purpose memory control circuit can be realized.
  • a memory control circuit can control a plurality of memories having logic interfaces supporting different source voltages from each other, and includes a control bus, a first data bus, a second data bus and a controller.
  • the control bus includes signal lines for transmitting an address signal and a control signal to and from a main memory which operates at the minimum source voltage among the plurality of memories.
  • the first data bus transmits a data signal to and from the main memory.
  • the second data bus transmits a data signal which conforms to the logic interface of a boot memory operating at a higher source voltage than the source voltage of the main memory among the plurality of memories.
  • the controller accesses the main memory to perform activation process of the memory control circuit.
  • the second data bus provided for the boot memory can be used as a bus for transmitting the initial data required for activation process. Therefore, the memory control circuit according to the present aspect does not need to have a second boot memory since it executes a slave operation of loading initial data for activation from the external controller, with the result that reduction in substrate area as well as reduction in power consumption can be realized.
  • the pins connected to the second data bus can be used as functional pins dedicated for loading of initial data, another functional pins are not necessary for the slave operation, which provides an advantage that the function is not restricted.
  • the controller includes first to third level converters.
  • the first level converter outputs to the control bus an address signal and a control signal obtained by converting voltage levels of internal signals in accordance with an input voltage defined by the logic interface of the main memory.
  • the second level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the boot memory, and sends/receives the data signal via the first data bus.
  • the third level converter converts voltage level of an input signal or an output signal in accordance with an input voltage or an output voltage defined by the logic interface of the controller, and receives the initial data via the second data bus.
  • a control system includes a memory control circuit according to the seventh or eighth aspect of the present invention, and an external controller for transmitting initial data required for the activation process to the memory control circuit.
  • FIG. 1 is a schematic configuration view showing a memory control circuit according to the first embodiment of the present invention
  • FIG. 2 is a schematic view showing an example of voltage levels at the output end and input end of signal
  • FIG. 3 is a schematic view showing an example of voltage levels at the output end and input end of signal
  • FIG. 4 is a schematic configuration view showing a memory control circuit according to a first modified example for the first embodiment
  • FIG. 5 is a schematic configuration view showing a memory control circuit according to a second modified example for the first embodiment
  • FIG. 6 is a schematic configuration view showing a memory control circuit according to the second embodiment of the present invention.
  • FIG. 7 is a schematic configuration view showing a memory control circuit according to a modified example for the second embodiment
  • FIG. 8 is a schematic configuration view showing a memory control circuit according to the third embodiment of the present invention.
  • FIG. 9 is a schematic configuration view showing a memory control circuit according to a modified example for the third embodiment.
  • FIG. 10 is a schematic configuration view showing a memory control system
  • FIG. 11 is a schematic configuration view showing a control system according to the fourth embodiment of the present invention.
  • FIG. 12 is a schematic configuration view of a control system according to a modified example for the fourth embodiment.
  • FIG. 13 is a schematic configuration view showing one example of a memory control circuit.
  • FIG. 14 is a schematic configuration view showing another example of a memory control circuit.
  • FIG. 1 is a schematic configuration view of a memory control circuit according to the first embodiment of the present invention.
  • This memory control circuit is an integrated circuit having a controller 1 A which controls two kinds of memories 13 and 14 having logic interfaces of different source voltages V DD via buses 10 , 11 and 12 .
  • the RAM 13 implemented by a DRAM (Dynamic Random Access Memory) or an SRAM, for example, can be used as a main memory for temporarily storing variables and data generated during execution of program.
  • the nonvolatile memory 14 implemented by a mask ROM or a flash memory, for example, stores read-only data such as a boot program required in activation of the system and initial data required in executing a program.
  • control bus 10 consisting of a plurality of signal lines for transmitting an address signal for designating an address on the memories 13 and 14 and a control signal required for writing and reading of data.
  • This control bus 10 is connected to a controlling input terminal of the RAM 13 and a controlling input terminal of the nonvolatile memory 14 , and shared by the memories 13 and 14 .
  • a data bus 11 consisting of a plurality of signal lines for transmitting write data or readout data of the RAM 13 , and this data bus 11 is connected with a data input/output terminal of the RAM 13 .
  • a data bus 12 consisting of a plurality of signal lines for transmitting write data or readout data of the nonvolatile memory 14 , and this data bus 12 is connected with a data input/output terminal of the nonvolatile memory 14 . Accordingly, two data buses 11 and 12 are individually disposed for the RAM 13 and the nonvolatile memory 14 .
  • the controller 1 A includes a MIU (memory interface unit) 3 for performing memory management of the RAM 13 and the nonvolatile memory 14 , a PAD circuit 6 for converting voltage level of input/output signal in conformance with the logic interface of the RAM 13 , a PAD circuit 7 for converting voltage level of input/output signal in conformance with the logic interface of the nonvolatile memory 14 , and a CPU (micro processor) 2 .
  • This CPU 2 loads program data stored in the nonvolatile memory 14 at the time of activation of the controller 1 A and uses the RAM (main memory) 13 as a work area for temporarily storing command groups and data being used during execution of the program data.
  • the MIU 3 is equipped with a memory controller 4 and a selector 5 .
  • the CPU 2 first issues an access request with respect to the MIU 3 .
  • the MIU 3 fetches an address signal AD 0 and a control signal CT 0 transferred via an internal bus (not shown) from the CPU 2 and outputs them to the PAD circuit 6 in predetermined timing.
  • a plurality of access requests can be inputted to the MIU 3 simultaneously.
  • the MIU 3 sets priority between each access request and gives an access approval to a related processing circuit in accordance with this priority. Then the MIU 3 outputs an address signal AD in and a control signal CT in transferred from that processing circuit to the PAD circuit 6 .
  • a level converter 6 A operates in synchronization with a control signal PC A supplied from the memory controller 4 , converts the internal voltage levels of the address signal AD in and the control signal CT in transferred from the memory controller 4 in conformance with the logic interface of the RAM 13 driven at low voltage, and outputs signals after conversion to the control bus 10 via the output port 8 A.
  • a level converter 6 B operates in synchronization with a control signal PC B supplied from the memory controller 4 , converts the internal voltage level of data DO outputted from the CPU 2 and inputted via the MIU 3 in conformance with the logic interface of the RAM 13 and outputs data after conversion RD to the data bus 11 via the input/output port 8 B. Also, the level converter 6 B may convert the voltage level of the data RD inputted from the data bus 11 via the input/output port 8 B into an internal voltage level, and output data after conversion RD in to the “0” side terminal of the selector 5 .
  • the selector 5 selects either one of the “0” side terminal or “1” side terminal in accordance with the logic level of a selection signal SC supplied from the memory controller 4 , and outputs data inputting to that terminal to the CPU 2 as election data DI. Therefore, the selector 5 outputs the data RD in inputting to the “0” side terminal to the CPU 2 when the selection signal SC of low level is supplied to the selector 5 .
  • data NVD read out from the nonvolatile memory 14 driven at high voltage travels the data bus 12 and inputs to the PAD circuit 7 via the input port 8 C.
  • a level converter 7 A of the PAD circuit 7 converts the voltage level of the input data NVD into an internal voltage level, and outputs data NVD in after conversion to the “1” side terminal of the selector 5 .
  • the selector 5 outputs the data NVD in inputted at its “1” side terminal to the CPU 2 while receiving the selection signal SC of high level.
  • the address signal and the control signal outputted from the controller 1 A are converted into signals conforming to the logic interface supporting low source voltage (hereinafter, referred to as low voltage interface) by the level converter 6 A, and thereafter transmitted to the RAM 13 and the nonvolatile memory 14 via the common control bus 10 . Therefore, it is possible to prevent a voltage higher than the input withstand pressure from being applied to the controlling input terminals of the memories 13 and 14 . In addition, since the number of signal lines for buses is reduced, it is possible to realize lower power consumption while reducing the number of terminals (pin number) of the input/output ports 8 A to 8 C at the controller 1 A end.
  • the data buses 11 and 12 are independently provided for the RAM 13 and the nonvolatile memory 14 , the data signal read out from the nonvolatile memory 14 driven at high voltage will not be transmitted to the RAM 13 driven at low voltage, making it possible to prevent malfunctions such as latch up from occurring in the RAM 13 .
  • the PAD circuit 7 is equipped with the level converter 7 A for input which converts only input signals since an assumption is made that the nonvolatile memory 14 driven at high voltage is used as a read only memory storing a program. Furthermore, when using a writable memory such as flash memory as the nonvolatile memory 14 , the PAD circuit 7 A may have a function of converting levels of not only input data (readout data) but also output data (write data) as is the case of the aforementioned level converter 6 B.
  • the nonvolatile memory 14 having a logic interface supporting high source voltages receives the output signal conforming to the low voltage interface, and has to determine whether the logic level of that signal is the high level or the low level.
  • high voltage interface receives the output signal conforming to the low voltage interface, and has to determine whether the logic level of that signal is the high level or the low level.
  • a range defining output voltages (V OH , V OL ) of low voltage interface is included in a range defining input voltages (V IH , V IL ) of high voltage interface.
  • the minimum value for output voltages of high level can be set at 2.15 V
  • the maximum value for output voltages of low level can be set at 0.55 V.
  • FIG. 3 is a view showing voltage levels at the output end according to the SSTL2 standard, and voltage levels at the input end according to the LVTTL standard.
  • the output end of the SSTL2 standard corresponds to the PAD circuit 6
  • the input end of the LVTTL standard corresponds to the nonvolatile memory 14 . As shown in FIG.
  • the memory control circuit according to the first modified example includes a controller 1 B for controlling two kinds of memories 24 and 25 having logic interfaces which are different in source voltage via buses 20 , 21 and 22 and a signal line 23 .
  • the second memory 25 is implemented by a nonvolatile memory 25 having a capacity of about 8M bytes at maximum and conforms to the high voltage interface standard (LVTTL standard) wherein operation source voltage is 3.3 V.
  • the controller 1 B includes a CPU 2 , a MIU 3 and PAD circuits 6 and 7 , and the PAD circuit 7 in this first modified example is further equipped with a level converter 7 B for converting the level of voltage of a control signal transmitted from the memory controller 4 .
  • This level converter 7 B operates in response to a control signal PC D supplied from the memory controller 4 .
  • This controller 1 B has output ports 8 A and 8 D for outputting an address signal and a control signal, and input/output ports 8 B and 8 C for inputting/outputting data from/to the memories 24 and 25 .
  • the control bus 20 Between the output port 8 A and the SRAM 24 is disposed the control bus 20 for transmitting an address signal and a control signal to and from the SRAM 24 . Since this control bus 20 is connected with a controlling input terminal of the SRAM 24 , and branches off in the course to be connected with a controlling input terminal of the nonvolatile memory 25 , the SRAM 24 and the nonvolatile memory 25 share this control bus 20 .
  • the control bus 20 consists of a total of 28-bit wide signal lines, concretely, 23-bit wide signal lines for transmitting address signals MA 0 , MA 1 , . . . , and MA 22 (MA[ 22 : 0 ]), 2-bit wide signal lines for transmitting output enable signals OEB 0 and OEB 1 (OEB[ 1 : 0 ]), 2-bit wide signal lines for transmitting write enable signals WEB 0 and WEB 1 (WEB[ 1 : 0 ]) and a one-bit wide signal line for transmitting a chip select signal CS 1 .
  • the data bus 21 connected to the input/output port 8 B connects with a data input/output terminal of the SRAM 24 and transmits data read out from the SRAM 24 and data to be written to the SRAM 24 .
  • This data bus 21 consists of a total of 16-bit wide signal lines, concretely, 16-bit wide signal lines for transmitting data signals MD 0 , MD 1 , . . . , and MD 15 (MD[ 15 : 0 ]).
  • the 1-bit wide signal line 23 connected with the output port 8 D is connected to a controlling input terminal of the nonvolatile memory 25 .
  • This signal line 23 transmits a chip select signal CS 2 .
  • the controller 1 B operates in the following manner when accessing the SRAM 24 .
  • the CPU 2 issues an access request to the SRAM 24 with respect to the MIU 3 .
  • the MIU 3 fetches an address signal AD 0 and a control signal CT 0 (address signal AD in and control signal CT in ) transferred from the CPU 2 , and outputs them to the PAD circuit 6 in predetermined timing.
  • the PAD circuit 6 converts the voltage levels of the address signal AD in and the control signal CT in inputted from MIU 3 and outputs signals after conversion to the control bus 20 via the output port 8 A.
  • the memory controller 4 controls so that the SRAM 24 and the nonvolatile memory 25 are not accessed simultaneously. Accordingly, during the period when the memory controller 4 accesses the SRAM 24 , the chip select signal CS 1 supplied to the SRAM 24 is kept at active high level. As a result of this, the SRAM 24 approves inputting of the address signals MA[ 22 : 0 ] and the control signals WEB[ 1 : 0 ].
  • the controller 1 B operates in the following manner when accessing the nonvolatile memory 25 .
  • the CPU 2 issues an access request to the nonvolatile memory 25 with respect to the memory controller 4 .
  • the memory controller 4 fetches an address signal AD 0 and a control signal CT 0 (signals AD in and CT in ) transferred from the CPU 2 , and outputs them to the PAD circuit 6 in predetermined timing.
  • the PAD circuit 6 converts the voltage levels of the signals AD in and CT in inputted from the MIU 3 and outputs signals after conversion to the control bus 20 via the output port 8 A.
  • the memory controller 4 keeps the chip select signal CS 1 to be supplied to the SRAM 24 at nonactive low level. As a result of this, all input signals to the SRAM 24 are masked.
  • control bus 20 can be shared by the SRAM 24 and the nonvolatile memory 25 having different operation source voltages V DD of logic interface, it is possible to reduce the pin number of the input/output ports 8 A to 8 D at the controller 1 C, and reduction of power consumption is realized.
  • FIG. 5 is a schematic configuration view of a memory control circuit according to this second modified example.
  • the configuration of this memory control circuit is almost as same as the circuit configuration for the first modified example shown in FIG. 4 except for the wire connecting the SDRAM 26 , the nonvolatile memory 27 and buses 30 and 31 .
  • elements denoted by the same reference numerals shown in FIG. 4 are regarded as having the same functions as the elements of the above first modified example, and detailed explanation of which will be omitted.
  • the memory control circuit according to the second modified example includes a controller 1 B′ having almost the same configuration as the controller 1 B shown in FIG. 4 .
  • the control bus 30 for transmitting an address signal and a control signal to the SDRAM 26 branches off to be introduced to the nonvolatile memory 27 , and the control bus 30 is shared with the memories 26 and 27 . Therefore, it is possible to reduce the pin number of the input/output ports 8 A and 8 B at the controller 1 B′, and the power consumption can be reduced.
  • the controller 1 C includes a CPU 2 , a MIU 3 and PAD circuits 6 and 7 . Between an output port 8 A of this controller 1 C and the SDRAM 26 is disposed a control bus 28 for transmitting an address signal and a control signal to and from the SDRAM 26 .
  • This control bus 28 is connected to a controlling input terminal of the SDRAM 26 and branches off in the course to be connected to a controlling input terminal of the nonvolatile memory 27 . Therefore, the SDRAM 26 and the nonvolatile memory 27 share this control bus 28 .
  • the input/output port 8 B of the controller 1 C is connected to a data bus 29 having a 16-bit width for transmitting data signals MD 0 , MD 1 , . . . , and MD 15 (MD[ 15 : 0 ]) to and from the SDRAM 26 .
  • This data bus 29 branches in the course to be connected to an address input terminal of the nonvolatile memory 27 .
  • the signal lines for transmission of address signals MA 15 , . . . , and MA 30 (MA[ 30 : 15 ]) are allocated to the signal lines for transmission of data signals MD[ 15 : 0 ]
  • the nonvolatile memory 27 is supplied with a total of 31 bits of address signals MA[ 30 : 0 ].
  • a data bus 22 having a 8-bit width for transmitting data signals RMD 0 , RMD 1 , . . . , and RMD 7 (RMD[ 7 : 0 ]).
  • the signal line 23 of 1-bit width connected to the output port 8 D also transmits a chip select signal CS 2 to the nonvolatile memory 27 .
  • the controller 1 C operates in the following manner when accessing the SDRAM 26 .
  • the CPU 2 issues an access request to the SDRAM 26 with respect to the MIU 3 .
  • the MIU 3 fetches an address signal AD 0 and a control signal CT 0 transferred from the CPU 2 , and output them to the PAD circuit 6 in predetermined timing.
  • the PAD circuit 6 converts the voltage levels of the address signal AD in and the control signal CT in inputted from the MIU 3 , and outputs signals after conversion to the control bus 28 via the output port 8 A.
  • the SDRAM 26 and the nonvolatile memory 27 share the control bus 28 , whereby the control signals MOE[ 1 : 0 ] for the nonvolatile memory 27 are allocated to the signal lines for transmission of the control signals DQM[ 1 : 0 ] for the SDRAM 26 , and the address signals MA[ 14 : 13 ] for the nonvolatile memory 27 are allocated to the signal lines for transmission of the control signals MBA[ 1 : 0 ] for the SDRAM 26 .
  • the memories 26 and 27 share the data bus 29 , whereby the address signals MA[ 30 : 15 ] for the nonvolatile memory 27 are allocated to the signal lines for transmission of the data signals MD[ 15 : 0 ] for the SDRAM 26 . Accordingly, the bit width of bus required for accessing the memories 26 , 27 is decreased, so that it possible to reduce the number of pins at the controller 1 C and to reduce the power consumption, as well as to extend the addressing range of the nonvolatile memory 27 .
  • signal lines for transmitting the address signal MA[ 12 : 0 ] are connected to the address input terminal of the SDRAM 26 , while other signal lines for transmitting the control signals DQM[ 1 : 0 ], WE, CS 1 , RAS, CAS, MBA[ 1 : 0 ], MCLKE and MCLK are connected to the controlling input terminal of the SDRAM 26 .
  • signal lines for transmitting the address signals MA[ 12 : 0 ], the address signals MA[ 14 : 13 ] allocated to the bank address signals MBA[ 1 : 0 ], the output enable signals MOE[ 1 : 0 ] allocated to the mask signals DQM[ 1 : 0 ], and the write enable signal WE are connected to the address input terminal and the controlling input terminal of the nonvolatile memory 27 ′.
  • the nonvolatile memory 27 ′ has a capacity of about 8M bytes at maximum and conforms to the standard wherein source voltage is 3.3 V (LVTTL standard). Therefore, in comparison with the second embodiment, the memory capacity of the nonvolatile memory 27 ′ is reduced, and the number of address input terminal of the nonvolatile memory 27 ′ is reduced to 23 .
  • the signal lines of the data bus 29 branching to the nonvolatile memory 27 ′ are connected so that they transmit 8-bit wide address signals MA[ 22 : 15 ] allocated to the signal lines for transmission of data signals MD[ 15 : 8 ].
  • FIG. 8 is a schematic configuration view of a memory control circuit according to the third embodiment.
  • This memory control circuit includes a controller 1 D for controlling an SDRAM 26 having a capacity of about 32M bytes at maximum and conforming to the standard wherein source voltage is 2.5 V (SSTL2 standard), and a nonvolatile memory 27 having a capacity of about 8M bytes at maximum and conforming to the standard wherein source voltage is 3.3 V (LVTTL standard).
  • the controller 1 D includes a PAD circuit 6 having three kinds of level converters 6 A, 6 B and 6 C supporting the low voltage interface of the SDRAM 26 , a PAD circuit 7 having a level converter 7 A supporting the high voltage interface of the nonvolatile memory 27 , a CPU 2 , a MIU 3 , and a GPIO function part (General Purpose Input/Output Function Part) 39 .
  • the GPIO function part 39 has a general-purpose data input/output function for peripheral devices.
  • the selector 5 selects data MD in inputted from the “0” side terminal and outputs it to the CPU 2 , whereas during receiving the high level signal, the selector 5 selects data RMD in inputted from the “1” side terminal and outputs it to the CPU 2 .
  • the controller ID has input/output ports 8 A to 8 D, and between the output port 8 A and the SDRAM 26 is disposed a control bus 34 for transmitting an address signal and a control signal.
  • This control bus 34 branches in the course to be connected to the nonvolatile memory 27 .
  • the control bus 34 also consists of a total of 23-bit wide signal lines for transmitting the above-mentioned address signals MA[ 12 : 0 ], mask signals DQM[ 1 : 0 ], write enable signal WE, chip select signal CS 1 , row address strobe signal RAS, column address strobe signal CAS, bank address signals MBA[ 1 : 0 ], clock enable signal MCLKE and clock signal MCLK to the SDRAM 26 .
  • a part of signal lines constituting the control bus 34 branches off to be connected to the nonvolatile memory 27 . That is, the signal lines for transmitting the address signals MA[ 12 : 0 ], mask signals DQM[ 1 : 0 ], bank address signals MBA[ 1 : 0 ] and write enable signal WE branch off to be connected to the input terminal of the nonvolatile memory 27 .
  • the output enable signals MOE[ 1 : 0 ] are allocated to the signal lines for transmission of mask signals DQM[ 1 : 0 ]
  • the address signals MA[ 14 : 13 ] are allocated to the signal lines for transmission of bank address signals MBA[ 1 : 0 ].
  • signal lines having a 16-bit width for transmitting data signals MD[ 15 : 0 ].
  • 8-bit wide signal lines for transmission of data signals MD[ 15 : 8 ] branch off to be connected to the address input terminal of the nonvolatile memory 27 , and during accessing to the nonvolatile memory 27 , the address signals MA[ 22 : 15 ] are allocated to these signal lines for transmission of data signals MD[ 15 : 8 ].
  • the output port 8 C of the controller ID is connected to a signal line 36 for transmitting the chip select signal CS 2 to the nonvolatile memory 27 .
  • the input port 8 D is connected to an 8-bit wide data bus 37 for transmitting the data signals RMD[ 7 : 0 ] read out from the nonvolatile memory 27 .
  • the operation during the period of accessing the SDRAM 26 from the controller ID is as follows.
  • the CPU 2 issues an access request to the SDRAM 26 with respect to the MIU 3 .
  • the MIU 3 fetches the an address signal AD 0 and a control signal CT 0 transferred from the CPU 2 and outputs them to the level converter 6 A in predetermined timing.
  • the level converter 6 A converts voltage levels of the address signal AD in inputted from the memory controller 4 and the control signal CT in in conformance with the low voltage interface of the SDRAM 26 , and outputs signals after conversion to the control bus 34 via the output port 8 A.
  • a write command is issued by combination of the above control signals CT in .
  • Write data DO outputted from the CPU 2 is transferred to the level converter 6 B via the MIU 3 .
  • the level converter 6 B converts the voltage level of the inputting write data DO in timing according to the control signal PC A supplied from the memory controller 4 , and outputs the resultant data to a data bus 35 via the input/output port 8 B.
  • the SDRAM 26 executes an operation of writing the data signals MD[ 15 : 0 ] transmitted through the data bus 35 in response to the above write command into a storage area designated by the address signals MA[ 12 : 0 ].
  • a readout command is issued by combination of the above control signal CT in .
  • the SDRAM 26 reads out the data signals MD[ 15 : 0 ] from a storage area designated by the address signals MA[ 12 : 0 ] in accordance with the readout command and outputs them to the data bus 35 .
  • the data signals MD[ 15 : 0 ] inputted to the input/output port 8 B are subjected to conversion of voltage level by means of the level converter 6 B and outputted to the “0” side terminal of the selector 5 as readout data MD in .
  • the operation during access to the nonvolatile memory 27 from the controller ID is as follows.
  • the CPU 2 issues an access request to the nonvolatile memory 27 with respect to the MIU 3 .
  • the MIU 3 fetches an address signal AD 0 and a control signal CT 0 transferred from the CPU 2 , and outputs them to the level converter 6 A and the level converter 6 C in predetermined timing.
  • the level converter 6 A converts voltage levels of the address signal AD in and the control signal CT in inputted from the memory controller 4 in conformance with the low voltage interface of the SDRAM 26 in timing of control signal PC A supplied from the memory controller 4 and outputs signals after conversion to the control bus 34 .
  • the voltage level of the chip select signal CS in inputted from the memory controller 4 is converted in timing of the control signal PC E supplied from the memory controller 4 in conformance with the low voltage interface and a chip select signal CS 2 after conversion is outputted to the signal line 36 via the input port 8 C.
  • the SDRAM 26 is in a nonactive state where input signals are masked.
  • the nonvolatile memory 27 reads out data based on the address signals MA[ 22 : 0 ] and the control signals MOE[ 1 : 0 ] transmitted through the control bus 34 and the data bus 35 and output the data to the data bus 37 .
  • the data signals RMD[ 7 : 0 ] inputted to the input port 8 D are subjected to conversion of voltage level by means of the level converter 7 A, and outputted to the GPIO function part 39 and the “1” side terminal of the selector 5 as readout data RMD in .
  • the selector 5 outputs the readout data RMD in inputting to the “1” side terminal to the CPU 2 based on the high level selection signal supplied from the AND gate 32 . Also, the readout data RMD in may be outputted to peripheral devices via the GPIO function part 39 .
  • FIG. 9 is a schematic configuration view of a memory control circuit according to the present modified example.
  • elements denoted by the same reference numerals shown in FIG. 8 have almost the same functions as the elements as described above, and detailed explanation of which will be omitted.
  • the memory control circuit comprises the controller 1 D in the above-described third embodiment, memories 26 and 27 ′′ supporting the standard wherein source voltage is 2.5 V (SSTL2 standard), buses 34 and 35 , and a control line 36 .
  • the logic interface for the two kinds of memories 26 and 27 ′′ for the controller 1 D is the same. Therefore, by branching the data bus 35 , access to the data input/output terminal of the nonvolatile memory 27 ′′ can be achieved. Therefore, the SDRAM 26 and the nonvolatile memory 27 ′′ share the data bus 35 .
  • the 16-bit wide data bus 35 connecting the input/output port 8 B of the controller 1 D and the SDRAM 26 branches off in the same manner as the third embodiment described above to be connected to the address input terminal of the nonvolatile memory 27 ′′.
  • 8-bit signals can be supplied to the input port 8 D.
  • the 8-bit signal is then supplied to the CPU 2 via the level converter 7 A and the selector 5 , with the result that the CPU 2 can perform various controls in response to detection of the 8-bit signal.
  • buses 34 and 35 for transmitting address signals, control signals and data signals can be shared when two kinds of memories 26 , 27 ′′ conforming to the same standard of voltage are used, it is possible to use the bus 37 that used to be a data bus in the third embodiment, for signal transmission other than sending and receiving of control signals and data signals supplied to the memories.
  • FIG. 10 is a schematic view showing one example of configuration of a control system using the memory control circuit according to the first embodiment. First the configuration of the control system shown in FIG. 10 is described in detail, and then problems associated with that configuration will be explained.
  • the controller 1 A functions as a sub system for a main controller 50 A.
  • the main controller 50 A is equipped with a memory controller 53 having a similar function as the memory controller 4 of the controller 1 A.
  • a control bus 56 connected to an output port 55 A of the main controller 50 A branches off to be connected to the RAM 60 and the nonvolatile memory 61
  • a data bus 57 connected to an input/output port 55 B branches off to be connected to the RAM 60 and the nonvolatile memory 61 .
  • the PAD circuit 54 includes two kinds of level converters 54 A and 54 B controlled by control signals PC A and PC B transmitted from the memory controller 53 .
  • the level converter 54 A has a function of converting voltage levels of internal signals CT in and AD in outputted from the MIU 52 and outputting signals after conversion to the control bus 56 via the output port 55 A.
  • the other level converter 54 B has a function of converting voltage level of output data DO and outputting the signal after conversion to the data bus 57 via the input/output port 55 B, as well as a function of converting voltage level of an input signal from the input/output port 55 B to the internal voltage level and outputting input data DI.
  • main controller 50 A and controller 1 A execute processes in synchronization with each other while sending/receiving processing data T D to/from each other.
  • the controller 1 A and the main controller 50 A are connected with various kinds of peripheral circuits P 1 , P 2 and P 3 via I/O circuits (not shown), and have a function of processing data inputted from these peripheral devices P 1 , P 2 and P 3 .
  • a digital signal processing circuit such as compression/expansion processing circuit for executing compression coding and decoding of data and the like as the peripheral circuits P 1 , P 2 and P 3 can be considered.
  • the main controller 50 A processes a digital image signal inputted from the CCD pickup apparatus and transfers it to the controller 1 A as transaction data T D , and thereafter the controller 1 A may control the compression/expansion circuit which is the peripheral device P 1 to perform compression coding of the input data T D .
  • the control system having the configuration as described above can be activated in the manner as summarized below.
  • the CPU 51 of the main controller 50 A executes a command for loading a boot program from the nonvolatile memory 61 in response to a reset signal. That is, the CPU 51 issues an access request to the nonvolatile memory 61 with respect to the memory controller 53 , and the memory controller 53 fetches an address signal AD 0 and a control signal CT 0 transferred from the CPU 51 after approving the access request and outputs these to the PAD circuit 54 as an address signal AD in and a control signal CT in in predetermined timing.
  • the level converter 54 A of the PAD circuit 54 converts voltage levels of the signals AD in and CT in inputted from the MIU 52 , and outputs signals after conversion to the control bus 56 via the output port 55 A.
  • a boot program required for activation of a main system is read out from the nonvolatile memory 61 and outputted to the data bus 57 . Thereafter, the boot program is inputted to the PAD circuit 54 via the input/output port 55 B, and subjected to level conversion at the level converter 54 B. As a result of the level conversion, readout data DI is then loaded to the CPU 51 .
  • the CPU 51 executes the program thus loaded using the RAM 60 as a work area to initiate and activate the main system.
  • the CPU 51 outputs data DO such as commands generated at the time of execution of that boot program to the data bus 57 via the level converter 54 B and the input/output port 55 B for temporarily storing in the RAM 60 .
  • the CPU 51 also reads out data temporarily stored in the RAM 60 via the input/output port 55 B and the level converter 54 B to load it as data DO.
  • the CPU 2 of the controller 1 A also loads a boot program stored in the nonvolatile memory 14 in response to a reset signal at the time of turning on the power, executes the boot program while using the RAM 13 as a work area to initiate and activate the sub system.
  • the main controller 50 A constituting the main system and the controller 1 A constituting the sub system individually have the respective nonvolatile memories 14 and 61 .
  • These two nonvolatile memories 14 and 61 pose the problem that the two IC chips increase the substrate area and increase the power consumption.
  • This problem is successfully solved by the control system according to the fourth embodiment shown in FIG. 11 .
  • elements denoted by the same reference numerals shown in FIG. 10 are regarded as having the same functions as the elements of the above first modified example, and detailed explanation of which will be omitted.
  • the control system includes a main controller 50 B constituting a main system and a controller 1 E constituting a sub system, and the controller 1 E functions as a slave circuit of the main controller 50 B.
  • the nonvolatile memory 61 of the main system stores a first boot program for activation of the main system and a second program for activation of the sub system, and the sub system is activated by controlling the main system.
  • the control system shown in FIG. 11 is activated in the manner as follows. First, as the power of this control system is turned on, the CPU 51 is reset in the same activation manner as described above. Next, the CPU 51 loads the first boot program stored in the nonvolatile memory 61 and executes this first boot program to initiate and activate the main system.
  • the CPU 51 reads out the second boot program stored in the nonvolatile memory 61 and executes a command to be transferred to the controller 1 E. That is, the CPU 51 issues an access request so as to load the second boot program from the nonvolatile memory 61 with respect to the memory controller 53 .
  • the memory controller 53 accesses the nonvolatile memory 61 via the control bus 56 .
  • the second boot program read out from the nonvolatile memory 61 is transmitted through the data bus 57 and inputted to the level converter 54 B via the input/output port 55 B.
  • the level converter 54 B converts the level of the data signal of the second boot program and outputs it to the memory controller 53 .
  • the memory controller 53 outputs the data signal D out of the second boot program thus loaded to the output port 55 C via an output circuit 58 .
  • the output port 55 C and the input port 8 C of the controller 1 E of the sub system are connected via the data bus 12 .
  • a data signal outputted from the output port 55 C travels the data bus 12 and inputs to the PAD circuit 7 via the input port 8 C of the sub system.
  • the resultant data signal D in is outputted to the memory controller 4 .
  • the CPU 51 of the main controller 50 B issues a load control signal L C with respect to the memory controller 4 of the controller 1 E and controls so that the data signal D in of the second boot program outputted from the PAD circuit 7 is fetched.
  • the memory controller 4 outputs the data signal D in thus fetched to the level converter 6 B in predetermined timing.
  • the data signal D in is then subjected to level conversion at the level converter 6 B, outputted from the input/output port 8 B, and inputted to the RAM 13 through the data bus 11 .
  • the second boot program is written into the RAM 13 , and the CPU 2 loads the second boot program from the RAM 13 to initiate and activate the sub system.
  • the controller 1 E of the sub system since the controller 1 E of the sub system has a slave function of loading the second boot program stored in the nonvolatile memory 61 of the main system to be activated in response to the control of the main system, it can operate without requiring a memory storing a boot program at the sub system. Therefore, according this control system, it is possible to reduce the area of the substrate, and reduce the power consumption compared with the control system shown in FIG. 10 .
  • the data bus 12 connected to the input port 8 C of the controller 1 E is originally designed for connection with a memory storing a boot program, however, by using this as a transmission path connecting between the controller 1 E and the main controller 50 B as shown in the fourth embodiment, it is possible to readily construct a sub system which loads a boot program from a main system.
  • FIG. 12 is a view showing a modified example for the control system according to the fourth embodiment as described above.
  • the control system shown in FIG. 12 differs from the control system shown in FIG. 11 in that it lacks the output circuit 58 and the output port 55 C provided in the main controller 50 B shown in FIG. 11, while alternatively, the data bus 12 connected to the input port 8 C of the controller 1 E branches off the control bus 56 of the main system.
  • Other configurations are the same in these systems.

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CN105190584B (zh) * 2013-03-07 2018-10-30 高通股份有限公司 用于基于总线速度选择性地终接双向总线上的信号的方法和装置
US20150194959A1 (en) * 2013-03-07 2015-07-09 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed
US20140253173A1 (en) * 2013-03-07 2014-09-11 Qualcomm Incorporated Method and apparatus for selectively terminating signals on a bidirectional bus based on bus speed

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