JP3735696B2 - 半導体メモリ装置のテスト回路及びテスト方法 - Google Patents

半導体メモリ装置のテスト回路及びテスト方法 Download PDF

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Publication number
JP3735696B2
JP3735696B2 JP30652796A JP30652796A JP3735696B2 JP 3735696 B2 JP3735696 B2 JP 3735696B2 JP 30652796 A JP30652796 A JP 30652796A JP 30652796 A JP30652796 A JP 30652796A JP 3735696 B2 JP3735696 B2 JP 3735696B2
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JP
Japan
Prior art keywords
column address
test
data
clock
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP30652796A
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English (en)
Japanese (ja)
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JPH09171700A (ja
Inventor
哲佑 朴
秀仁 趙
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH09171700A publication Critical patent/JPH09171700A/ja
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Publication of JP3735696B2 publication Critical patent/JP3735696B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C29/56012—Timing aspects, clock generation, synchronisation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
    • G11C2029/5602—Interface to device under test

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
JP30652796A 1995-11-16 1996-11-18 半導体メモリ装置のテスト回路及びテスト方法 Expired - Fee Related JP3735696B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1995P41674 1995-11-16
KR1019950041674A KR0172423B1 (ko) 1995-11-16 1995-11-16 고주파수 동작을 하는 반도체 메모리 장치의 테스트회로 및 테스트 방법

Publications (2)

Publication Number Publication Date
JPH09171700A JPH09171700A (ja) 1997-06-30
JP3735696B2 true JP3735696B2 (ja) 2006-01-18

Family

ID=19434348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30652796A Expired - Fee Related JP3735696B2 (ja) 1995-11-16 1996-11-18 半導体メモリ装置のテスト回路及びテスト方法

Country Status (3)

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JP (1) JP3735696B2 (ko)
KR (1) KR0172423B1 (ko)
TW (1) TW307828B (ko)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11144497A (ja) * 1997-11-13 1999-05-28 Mitsubishi Electric Corp 同期型半導体記憶装置
JPH11154103A (ja) 1997-11-20 1999-06-08 Mitsubishi Electric Corp 半導体集積回路装置
KR100532388B1 (ko) * 1998-08-04 2006-01-27 삼성전자주식회사 직렬 출력 비교기를 갖는 메모리 집적회로
US6393435B1 (en) 1999-09-22 2002-05-21 International Business Machines, Corporation Method and means for evaluating the performance of a database system referencing files external to the database system
JP4115676B2 (ja) * 2001-03-16 2008-07-09 株式会社東芝 半導体記憶装置
KR100442965B1 (ko) * 2001-12-29 2004-08-04 주식회사 하이닉스반도체 반도체 메모리장치의 내부 프리차지 펄스신호 발생회로
JP2005209239A (ja) * 2004-01-20 2005-08-04 Nec Electronics Corp 半導体集積回路装置
KR100588595B1 (ko) * 2005-04-22 2006-06-14 삼성전자주식회사 반도체 메모리 장치의 내부 클록 생성방법 및 이를 이용한반도체 메모리 장치
KR100748461B1 (ko) * 2006-09-13 2007-08-13 주식회사 하이닉스반도체 반도체 메모리 장치의 데이터 입력 회로 및 방법
KR100825779B1 (ko) * 2006-09-28 2008-04-29 삼성전자주식회사 반도체 메모리장치 및 이에 대한 웨이퍼 레벨 테스트 방법
KR102471531B1 (ko) * 2017-12-21 2022-11-28 에스케이하이닉스 주식회사 저속 동작 환경에서 고속 테스트를 수행할 수 있는 반도체 장치 및 시스템
CN111128257B (zh) * 2018-10-30 2024-10-01 长鑫存储技术有限公司 电源调节电路及方法、存储器

Also Published As

Publication number Publication date
TW307828B (ko) 1997-06-11
KR0172423B1 (ko) 1999-03-30
JPH09171700A (ja) 1997-06-30
KR970029883A (ko) 1997-06-26

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