JP3681741B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP3681741B2 JP3681741B2 JP2004001886A JP2004001886A JP3681741B2 JP 3681741 B2 JP3681741 B2 JP 3681741B2 JP 2004001886 A JP2004001886 A JP 2004001886A JP 2004001886 A JP2004001886 A JP 2004001886A JP 3681741 B2 JP3681741 B2 JP 3681741B2
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- 239000004065 semiconductor Substances 0.000 title claims description 153
- 238000009792 diffusion process Methods 0.000 claims description 278
- 239000012535 impurity Substances 0.000 claims description 58
- 230000015556 catabolic process Effects 0.000 claims description 40
- 239000000463 material Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 description 173
- 239000010408 film Substances 0.000 description 154
- 238000004519 manufacturing process Methods 0.000 description 28
- 238000010586 diagram Methods 0.000 description 23
- 239000000758 substrate Substances 0.000 description 14
- 239000013078 crystal Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000010409 thin film Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Description
請求項2記載の発明は、前記各ベース拡散領域は長手方向を有し、前記長手方向が互いに平行に配置され、前記埋込領域は前記各ベース拡散領域の長手方向に沿って互いに平行に配置された請求項1記載の半導体装置である。
請求項3記載の発明は、前記各埋込領域は、前記抵抗層に形成された活性溝と、前記活性溝内に充填された第2導電型の半導体材料を有する請求項1又は請求項2のいずれか1項記載の半導体装置である。
請求項4記載の発明は、前記各埋込領域の幅はそれぞれ等しい請求項2乃至請求項3のいずれか1項記載の半導体装置である。
請求項5記載の発明は、前記各埋込領域の長さが等しい請求項2乃至請求項4のいずれか1項記載の半導体装置である。
請求項6記載の発明は、前記ベース拡散領域を取り囲むリング状の複数の耐圧溝と、前記耐圧溝内に配置された第2導電型の半導体材料とを有する請求項1乃至請求項5のいずれか1項記載の半導体装置である。
請求項7記載の発明は、前記ソース拡散領域と前記ベース拡散領域に電気的に接続されたソース電極膜を有する請求項1乃至請求項6のいずれか1項記載の半導体装置である。
請求項8記載の発明は、前記抵抗層の前記ベース拡散領域が形成された面とは反対側の面には、前記抵抗層と同じ導電型で前記抵抗層よりも高濃度のドレイン層が配置された請求項1乃至請求項7のいずれか1項記載の半導体装置である。
請求項9記載の発明は、前記抵抗層の前記ベース拡散領域が形成された面とは反対側の面には、前記抵抗層とは反対の導電型のコレクタ層が配置された請求項1乃至請求項7のいずれか1項記載の半導体装置である。
請求項10記載の発明は、前記抵抗層の前記ベース拡散領域が形成された面とは反対側の面には、前記抵抗層とショットキー接合を形成するショットキー電極膜が配置された請求項1乃至請求項7のいずれか1項記載の半導体装置である。
請求項11記載の発明は、前記抵抗層の前記ベース拡散領域が形成された側の表面に、前記抵抗層と電気的に接続され、前記ソース電極膜とは絶縁されたドレイン電極膜が配置された請求項7記載の半導体装置である。
成長層12のうち、その内部表面であって、半導体装置1の中央位置には、成長層12よりも高濃度の第1導電型の導電層14が形成されており、成長層12と導電層14とでMOSトランジスタのドレインである抵抗層15が構成されている。本発明には導電層14を有さない半導体装置も含まれるが、その場合、成長層12によって抵抗層15が構成される。
上記(1)式から高さHと長さLを消去すると、
{Wm1×(n−1)+Wm2)}×Nd = Wt×n×Na ……(2)
となる。
いずれにしろ、破壊が生じやすい位置(d)ではアバランシェ降伏は発生しない。
図1(a)〜図26(a)は、上記のようなベース拡散領域17aが配置される活性領域の工程に沿った断面図であり、図1(b)〜図26(b)は、活性領域の外周付近の一部と、活性領域を取り囲む耐圧領域の断面図である。
活性溝43aの平面形状は細長開口42aと同じく細長の長方形であり、耐圧溝43bの形状はリング状開口42bと同じ四角リングである。
各ベース拡散領域17aは、四隅が丸く、長辺が埋込領域44aが伸びる方向に沿った長方形である。
オーミック拡散領域20とソース拡散領域21の平面形状の大きさはベース拡散領域17aよりも小さく、また、それらの深さはベース拡散領域17aの深さよりも浅い。オーミック拡散領域20とソース拡散領域21は、ベース拡散領域17aの内側に位置しており、導電領域14や成長層12とは接触していない。
ゲート電極膜36がしきい値電圧未満の電圧になると遮断する。
15……抵抗層
17a……ベース拡散領域
21……ソース拡散領域
22……チャネル領域
34……ゲート絶縁膜
36……ゲート電極膜
38……ソース電極膜
40a……半導体材料
43a……活性溝
44a……埋込領域
Wm1、Wm2……抵抗層の幅
Claims (11)
- 第1導電型の抵抗層と、
前記抵抗層の内部の表面付近に形成され、互いに離間して位置する第2導電型の複数のベース拡散領域と、
前記各ベース拡散領域の縁よりも内側の領域の前記各ベース拡散領域内部の表付近にそれぞれ形成され、前記各ベース拡散領域よりも浅い第1導電型のソース拡散領域と、
前記各ベース拡散領域の縁付近であって、前記各ベース拡散領域の縁と前記各ソース拡散領域の縁の間のチャネル領域と、
少なくとも前記各チャネル領域上に位置するゲート絶縁膜と、
前記ゲート絶縁膜上に位置するゲート電極膜と、
前記各ベース拡散領域底面に複数個ずつ配置され、前記各ベース拡散領域にそれぞれ接続された複数の第2導電型の埋込領域を有し、
隣接する2個一組のベース拡散領域のうち、一方のベース拡散領域の幅方向中央位置から他方のベース拡散領域の幅方向中央位置までの間であって、ベース拡散領域の深さよりも深く、埋込領域の底面よりも浅い範囲では、第1導電型の不純物量と第2導電型の不純物量とが等しくされ、且つ、前記埋込領域の内部が空乏層で満たされる電圧では前記埋込領域と前記抵抗層間のPN接合部はアバランシェ降伏を起こさないように設定され、
同じ前記ベース拡散領域の底面に隣接して位置する前記埋込領域の間の部分の前記抵抗層の幅Wm1は、異なる前記ベース拡散領域の底面にそれぞれ位置し互いに隣接する前記埋込領域で挟まれた部分の前記抵抗層の幅Wm2よりも大きく形成された半導体装置。 - 前記各ベース拡散領域は長手方向を有し、前記長手方向が互いに平行に配置され、
前記埋込領域は前記各ベース拡散領域の長手方向に沿って互いに平行に配置された請求項1記載の半導体装置。 - 前記各埋込領域は、前記抵抗層に形成された活性溝と、前記活性溝内に充填された第2導電型の半導体材料を有する請求項1又は請求項2のいずれか1項記載の半導体装置。
- 前記各埋込領域の幅はそれぞれ等しい請求項2乃至請求項3のいずれか1項記載の半導体装置。
- 前記各埋込領域の長さが等しい請求項2乃至請求項4のいずれか1項記載の半導体装置。
- 前記ベース拡散領域を取り囲むリング状の複数の耐圧溝と、
前記耐圧溝内に配置された第2導電型の半導体材料とを有する請求項1乃至請求項5のいずれか1項記載の半導体装置。 - 前記ソース拡散領域と前記ベース拡散領域に電気的に接続されたソース電極膜を有する請求項1乃至請求項6のいずれか1項記載の半導体装置。
- 前記抵抗層の前記ベース拡散領域が形成された面とは反対側の面には、前記抵抗層と同じ導電型で前記抵抗層よりも高濃度のドレイン層が配置された請求項1乃至請求項7のいずれか1項記載の半導体装置。
- 前記抵抗層の前記ベース拡散領域が形成された面とは反対側の面には、前記抵抗層とは反対の導電型のコレクタ層が配置された請求項1乃至請求項7のいずれか1項記載の半導体装置。
- 前記抵抗層の前記ベース拡散領域が形成された面とは反対側の面には、前記抵抗層とショットキー接合を形成するショットキー電極膜が配置された請求項1乃至請求項7のいずれか1項記載の半導体装置。
- 前記抵抗層の前記ベース拡散領域が形成された側の表面に、前記抵抗層と電気的に接続され、前記ソース電極膜とは絶縁されたドレイン電極膜が配置された請求項7記載の半導体装置。
Priority Applications (7)
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JP2004001886A JP3681741B2 (ja) | 2004-01-07 | 2004-01-07 | 半導体装置 |
PCT/JP2004/018480 WO2005067057A1 (ja) | 2004-01-07 | 2004-12-10 | 半導体装置 |
CNB2004800398545A CN100481501C (zh) | 2004-01-07 | 2004-12-10 | 半导体装置 |
KR1020067013577A KR100816702B1 (ko) | 2004-01-07 | 2004-12-10 | 반도체 장치 |
EP04821017A EP1705715B1 (en) | 2004-01-07 | 2004-12-10 | Semiconductor device |
US11/481,247 US7282764B2 (en) | 2004-01-07 | 2006-07-06 | Semiconductor device |
HK07107130.9A HK1099847A1 (en) | 2004-01-07 | 2007-07-03 | Semiconductor device |
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JP2004001886A JP3681741B2 (ja) | 2004-01-07 | 2004-01-07 | 半導体装置 |
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JP3681741B2 true JP3681741B2 (ja) | 2005-08-10 |
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US (1) | US7282764B2 (ja) |
EP (1) | EP1705715B1 (ja) |
JP (1) | JP3681741B2 (ja) |
KR (1) | KR100816702B1 (ja) |
CN (1) | CN100481501C (ja) |
HK (1) | HK1099847A1 (ja) |
WO (1) | WO2005067057A1 (ja) |
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JP3681741B2 (ja) * | 2004-01-07 | 2005-08-10 | 新電元工業株式会社 | 半導体装置 |
JP6092680B2 (ja) * | 2013-03-26 | 2017-03-08 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JP6092749B2 (ja) * | 2013-10-17 | 2017-03-08 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
CN108574012B (zh) * | 2017-03-08 | 2021-12-24 | 无锡华润华晶微电子有限公司 | 超结vdmos器件及其制备方法 |
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JPS62169368A (ja) * | 1985-09-10 | 1987-07-25 | Tdk Corp | 縦形半導体装置の製造方法 |
JPH0354868A (ja) * | 1989-07-21 | 1991-03-08 | Fuji Electric Co Ltd | Mos型半導体装置 |
JPH03155677A (ja) * | 1989-08-19 | 1991-07-03 | Fuji Electric Co Ltd | 伝導度変調型mosfet |
JPH03238871A (ja) * | 1990-02-15 | 1991-10-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3136885B2 (ja) * | 1994-02-02 | 2001-02-19 | 日産自動車株式会社 | パワーmosfet |
JP3524395B2 (ja) * | 1998-09-02 | 2004-05-10 | 株式会社ルネサステクノロジ | 半導体スイッチング素子 |
JP3636345B2 (ja) * | 2000-03-17 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | 半導体素子および半導体素子の製造方法 |
JP5134746B2 (ja) * | 2001-09-20 | 2013-01-30 | 新電元工業株式会社 | 電界効果トランジスタの製造方法 |
US6521954B1 (en) * | 2001-12-21 | 2003-02-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP3681741B2 (ja) * | 2004-01-07 | 2005-08-10 | 新電元工業株式会社 | 半導体装置 |
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- 2004-12-10 EP EP04821017A patent/EP1705715B1/en not_active Expired - Fee Related
- 2004-12-10 CN CNB2004800398545A patent/CN100481501C/zh not_active Expired - Fee Related
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CN100481501C (zh) | 2009-04-22 |
JP2005197439A (ja) | 2005-07-21 |
US7282764B2 (en) | 2007-10-16 |
EP1705715B1 (en) | 2012-08-22 |
US20070045776A1 (en) | 2007-03-01 |
EP1705715A1 (en) | 2006-09-27 |
CN1910758A (zh) | 2007-02-07 |
HK1099847A1 (en) | 2007-08-24 |
EP1705715A4 (en) | 2008-11-05 |
WO2005067057A1 (ja) | 2005-07-21 |
KR20060116017A (ko) | 2006-11-13 |
KR100816702B1 (ko) | 2008-03-27 |
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