WO2005067057A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- WO2005067057A1 WO2005067057A1 PCT/JP2004/018480 JP2004018480W WO2005067057A1 WO 2005067057 A1 WO2005067057 A1 WO 2005067057A1 JP 2004018480 W JP2004018480 W JP 2004018480W WO 2005067057 A1 WO2005067057 A1 WO 2005067057A1
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- base diffusion
- diffusion region
- region
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 148
- 238000009792 diffusion process Methods 0.000 claims abstract description 279
- 239000012535 impurity Substances 0.000 claims description 56
- 239000000463 material Substances 0.000 claims description 17
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
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- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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Definitions
- the present invention relates to a technique for increasing a breakdown voltage of a semiconductor device, and more particularly to a technique for improving a breakdown voltage and improving a breakdown voltage.
- reference numeral 101 denotes a conventional semiconductor device, in which an N-type resistive layer 112 having a large resistance is formed on an N-type substrate 111 having a small resistance by epitaxy.
- a plurality of P-type and elongated base diffusion regions 117 are formed on the inner surface of the resistance layer 112.
- N-type and elongated source diffusion regions 121 are arranged in parallel with the ohmic diffusion region 120.
- a portion of the inner surface of the base diffusion region 117 between the outer periphery of the source diffusion region 121 and the outer periphery of the base diffusion region 117 is a channel region 122, on which a gate insulating film 134 and a gate The electrode films 136 are arranged in this order.
- An interlayer insulating film 137 is disposed on the gate electrode film 136, and a source electrode film 138 in contact with the source diffusion region 121 and the ohmic diffusion region 120 is disposed on the interlayer insulating film 137. .
- the source electrode film 138 is separated from the gate electrode film 136 by an interlayer insulating film 137.
- the source electrode film 138 is electrically insulated from the gate electrode film 136 while being electrically connected to the source diffusion region 121, and the ohmic diffusion region 120 is formed in the base diffusion region 117. Are electrically connected via On the surface of the source electrode film 138, a protective film 139 is formed.
- a drain electrode film 130 is formed on the back surface of the substrate 111.
- a voltage equal to or higher than the threshold voltage is applied to the gate electrode film 136 with the source electrode film 138 grounded and a positive voltage applied to the drain electrode film 130, the channel region 122 is inverted to an N-type, and Source diffusion region 121 and resistance layer 112 are connected. This state is a conduction state, and a current flows from the drain electrode film 130 to the source electrode film 138.
- a P-type buried region 146 is arranged in contact with base diffusion region 117.
- the PN junction between the P-type region composed of the base diffusion region 117 and the buried region 146 and the N-type region composed of the resistance layer 112 is reverse-biased, and the base diffusion region From both 117 and the buried region 146, the depletion layer spreads greatly in both the P-type region and the N-type region.
- the embedded region 146 is an elongated region along the direction in which the elongated base diffusion region 117 extends, and one buried region 146 is arranged at a central position in the width direction of each base diffusion region 117.
- the base diffusion regions 117 are arranged in parallel with each other, and the buried regions 146 are also in parallel with each other.
- the depletion layer fills the portion of the resistance layer 112 sandwiched between the buried regions 146.
- the amount of N-type impurities contained in the portion of resistance layer 112 sandwiched between buried regions 146 is set to be equal to the amount of P-type impurities contained in buried regions 146! In this case, when the portion between the buried regions 146 of the resistance layer 112 is filled with the depletion layer, the inside of the buried region 146 is also filled with the depletion layer.
- the bottom surface of base diffusion region 117 is filled with a depletion layer up to the lower end of buried region 146, and the bottom surface of the depletion layer is flat.
- a diffusion structure giving the amount of impurities forming a depletion layer is called a RESURF structure.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2003-101022
- Patent Document 2 Japanese Patent Application Laid-Open No. 2003-86800
- An object of the present invention is to provide a semiconductor device having high withstand voltage and high withstand voltage.
- the invention according to claim 1 includes a first conductive type resistive layer and a second conductive type resistive layer formed near the inner surface of the resistive layer and located apart from each other.
- each of the buried regions has a groove formed in the resistance layer, and a semiconductor material of a second conductivity type filled in the groove. Or the semiconductor device according to item 1.
- the invention according to claim 4 is the semiconductor device according to any one of claims 2 to 3, wherein each of the buried regions has an equal width.
- the invention according to claim 5 is the semiconductor device according to any one of claims 2 to 4, wherein the lengths of the respective buried regions are equal.
- the invention according to claim 6 is that, of a pair of adjacent base diffusion regions, a region between the center position in the width direction of one base diffusion region and the center position in the width direction of the other base diffusion region; In the range shallower than the depth of the diffusion region and shallower than the bottom surface of the buried region, the amount of impurities of the first conductivity type and the amount of impurities of the second conductivity type are substantially equal. 2.
- the invention according to claim 7 is the semiconductor device according to any one of claims 1 to 6, further comprising a source electrode film electrically connected to the source diffusion region and the base diffusion region.
- a drain layer having the same conductivity type as the resistance layer and a higher concentration than the resistance layer is formed on a surface of the resistance layer opposite to the surface on which the base diffusion region is formed.
- the invention according to claim 9 is configured such that a collector layer of a conductivity type opposite to the resistance layer is disposed on a surface of the resistance layer opposite to a surface on which the base diffusion region is formed.
- the present invention is configured as described above, and among a plurality of buried regions located on the bottom surface of the same base diffusion region, the distance Wm between adjacent buried regions is determined by the buried region.
- the width of the resistive layer is the same as the width Wm of the
- the distance Wm between adjacent embedding areas, and the distance Wm between adjacent embedding areas is the distance Wm between adjacent embedding areas
- the width Wm of the resistance layer sandwiched between the regions can be configured to be the same. Distance Wm
- the distance is larger than Wm, and the avalanche breakdown is
- the source diffusion region is arranged at a certain distance along the edge of the base diffusion region, and the source electrode film connected to the source diffusion region has a base diffusion region near the center in the width direction of the base diffusion region. It is electrically connected to the area.
- the avalanche current flowing due to the avalanche breakdown does not pass through the high resistance portion of the base diffusion region below the bottom surface of the source diffusion region, so that a high breakdown resistance can be obtained.
- the buried region is arranged in parallel along the longitudinal direction of the base diffusion region.
- a semiconductor element having high breakdown strength can be obtained.
- FIG. 2 (a), (b): diagrams for explaining the manufacturing process of the semiconductor device of the present invention
- FIG. 3 (a), (b): diagrams for explaining the manufacturing process of the semiconductor device of the present invention (3)
- FIG. 4 (a), (b): diagrams for explaining the manufacturing process of the semiconductor device of the present invention (4)
- FIG. 5 (a), (b): diagrams for explaining the manufacturing process of the semiconductor device of the present invention (5)
- FIG. 6 (a), (b): diagrams for explaining the manufacturing process of the semiconductor device of the present invention (6)
- FIG. 7 (a), (b): diagrams for explaining the manufacturing steps of the semiconductor device of the present invention (7)
- FIG. 8 (a), (b): diagrams for explaining the manufacturing steps of the semiconductor device of the present invention (8)
- FIG. 9 (a), (b): diagrams for explaining the manufacturing steps of the semiconductor device of the present invention (9)
- FIG. 10 (a), (b): diagrams for explaining the manufacturing process of the semiconductor device of the present invention (10)
- FIGS. Ll diagrams for explaining the manufacturing steps of the semiconductor device of the present invention (11) ⁇ 12] (a), (b): FIGS. 12 (a) and 12 (b) for explaining the manufacturing process of the semiconductor device of the present invention.
- FIG.30 B-B section view of Fig.8 (a), (b)
- FIG.31 C-C section view of Fig.17 (a), (b)
- one of the P-type and the N-type will be described as the first conductivity type, and the other will be described as the second conductivity type. If the first conductivity type is N-type, the second conductivity type is P-type.
- the second conductivity type is N-type.
- the semiconductor substrate and the semiconductor layer are made of single-crystal silicon, but may be made of another semiconductor material.
- Reference numeral 1 in FIGS. 27 and 28 indicates a semiconductor device according to a first example of the present invention.
- the semiconductor device 1 has a semiconductor support layer 11 of the first conductivity type.
- a plurality of semiconductor devices 1 of the present invention are formed in one wafer.
- the semiconductor device 1 is epitaxially grown on the surface of the semiconductor support layer 11 in a wafer state, thereby forming the first conductivity type.
- a growth layer 12 is formed.
- a conductive layer 14 of the first conductivity type having a higher concentration than the growth layer 12 is formed on the inner surface of the growth layer 12 at the center of the semiconductor device 1.
- the resistive layer 15 which is the drain of the MOS transistor is constituted by the conductive layer 12 and the conductive layer 14.
- the present invention includes a semiconductor device having no conductive layer 14, but in this case, the resistive layer 15 Is configured.
- a plurality of base diffusion regions 17a of the second conductivity type are formed at predetermined intervals.
- the depth of all the base diffusion regions 17a is the same, and is smaller than the depth of the conductive layer 14 here.
- a semiconductor device in which the depth of the conductive layer 14 is shallower than the base diffusion region 17a is also included in the present invention.
- each base diffusion region 17a Near the surface inside each base diffusion region 17a, a source diffusion region 21 of the first conductivity type and an ohmic diffusion region 20 of the second conductivity type having a higher surface concentration than the base diffusion region 17a are arranged. I have.
- the planar shape of the base diffusion region 17a, the planar shape of the source diffusion region 21, and the planar shape of the ohmic diffusion region 20 are each formed in an elongated shape such as a rectangle, and inside one base diffusion region 17a.
- One or two source diffusion regions 21 have their long sides arranged along the longitudinal direction of the base diffusion region 17a.
- the ohmic diffusion region 20 is located at the center in the width direction of each base diffusion region 17a, and its long side is arranged along the longitudinal direction of the base diffusion region 17a.
- the width and length of source diffusion region 21 and ohmic diffusion region 20 are smaller than the width and length of base diffusion region 17a, and source diffusion region 21 and ohmic diffusion region 20 are base diffusion regions. It is made shallower than 17a, and the source diffusion region 21 and the ohmic diffusion region 20 are arranged so as not to protrude from the base diffusion region 17a.
- the source diffusion region 21 and the base diffusion region 17a have opposite conductivity types, a pn junction is formed between the source diffusion region 21 and the base diffusion region 17a, and the ohmic diffusion region 20 and the base diffusion region 17a Are of the same conductivity type, the ohmic diffusion region 20 and the base diffusion region 17a are electrically connected to each other.
- the source diffusion region 21 is also separated from the base diffusion region 20 by a certain distance in terms of the long-side force, and within the base diffusion region 17a, the long side of the base diffusion region 17a and the long side of the source diffusion region 21 The portion between these is a channel region 22 where an inversion layer as described later is formed. Since the base diffusion region 17a and the source diffusion region 21 are elongated, the channel region 22 is also elongated.
- a gate insulating film 34 is disposed on the channel region 22. Gate insulation film 34 The gate insulating film 34 slightly protrudes on both sides in the width direction of the tunnel region 22, and therefore, the ends in the width direction of the gate insulating film 34 are located on the source diffusion region 21 and the resistance layer 15.
- a gate electrode film 36 is disposed on the surface of the gate insulating film 34, and an interlayer insulating film 37 is disposed on the gate electrode film 36.
- a source electrode film 38 is disposed on the interlayer insulating film 37. At least a part of the surface of the source diffusion region 21 and the surface of the ohmic diffusion region 20 are exposed, and the source electrode film 38 is also disposed on the exposed portion, and the source electrode film 38 is electrically connected to the source diffusion region 21 and the ohmic diffusion region 20. Connected.
- the base diffusion region 17a is connected to the source electrode film 38 via the ohmic diffusion region 20. Therefore, the source diffusion region 21 and the base diffusion region 17a are short-circuited by the source electrode film 38. Since the interlayer insulating film 37 is located between the source electrode film 38 and the gate electrode film 36, the source electrode film 38 and the gate electrode film 36 are insulated by the interlayer insulating film 37.
- a drain electrode film 30 is disposed on the surface of the semiconductor support layer 11 opposite to the surface on which the resistance layer 15 is disposed.
- the drain electrode film 30 and the semiconductor support layer 11 are in ohmic contact unlike the Schottky junction type IGBT described later, and the drain electrode film 30 and the semiconductor support layer 11 are electrically connected.
- the source electrode film 38 is grounded and a positive voltage is applied to the drain electrode film 30.
- a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode film 36, an inversion layer of a conductivity type opposite to the channel region 22 is formed on the inner surface of the channel region 22, and the source diffusion region 21 and the resistance Layer 15 is connected at its inversion layer and becomes conductive.
- the semiconductor support layer 11 functions as a drain layer. In a conductive state, the inversion layer, the resistance layer 15 and the drain layer (from the drain electrode film 30 toward the source electrode film 38). A current flows through the semiconductor support layer 11).
- an elongated groove 43a is formed in the resistance layer 15 (in this embodiment, the groove 43a is formed after forming the conductive region 14).
- the groove 43a may be formed before the formation of the conductive region 14), and as shown in FIG. 9 (a), the groove 43a is filled with a semiconductor material 40a of the second conductivity type.
- the buried region 44a is formed below the groove 43a and the portion below the base diffusion region 17a of the semiconductor material 4Oa.
- the upper part of the buried region 44a is connected to the base diffusion region 17a.
- a PN junction is formed between a region of the second conductivity type composed of base diffusion region 17a and buried region 44a and a region of the first conductivity type composed of resistive layer 15. When the PN junction is reverse-biased, a depletion layer spreads in the base diffusion region 17a and the resistance layer 15 and in the buried region 44a.
- the depth D of the groove 43a from the surface of the resistive layer 15 is a depth that does not reach the semiconductor support layer 11, and the base diffusion region 17a depth
- the base diffusion region 17a has its longitudinal direction arranged along the longitudinal direction of the groove 43a. Further, the base diffusion region 17a is formed to have a width straddling the plurality of grooves 43a, and as a result, two or more buried regions 44a are arranged at the bottom of each base diffusion region 17a. The number of buried regions 44a located on the bottom surface of each base diffusion region 17a is the same.
- Each base diffusion region 17a is parallel to each other, and a plurality of buried regions 44a located at the bottom of one base diffusion region 17a are arranged with respect to the long side of the base diffusion region 17a to which the tops thereof are connected. Are parallel. Therefore, each buried region 44a is parallel to each other. Also, the width of each buried region 44a is equal.
- connection between the buried region 44a and the base diffusion region 17a is located inside the base diffusion region 17a rather than the channel region 22. Therefore, immediately below the channel region 22, the buried region 44a is It doesn't exist! /
- the distance between the side surfaces of the buried region 44a facing each other is defined as the distance between the buried regions 44a, and the distance Wm between the buried regions 44a located below the bottom surface of the same base diffusion region 17a is equal.
- the distance Wm is equal between the buried regions 44a located on the bottom surfaces of the different base diffusion regions 17a. Therefore, for all base diffusion regions 17a, the distance Wm is
- FIG. 27 shows a case where two buried regions 44a are located on the bottom surface of one base diffusion region 17a, and the distance Wm is equal to two buried regions located on the same base diffusion region 17a bottom surface. 44a
- the distance Wm between the buried regions 44a located on the bottom surfaces of the different base diffusion regions 17a and facing each other is determined by each base diffusion region.
- the distance Wm between the buried regions 44a located on the bottom surfaces of the different base diffusion regions 17a and facing each other is not necessarily equal.
- each embedding area 44a is represented by an equal sign Wt. Further, the distance between the depth D of the base diffusion region 17a and the depth D of the bottom surface of the buried region 44a, that is, the height D—D of the buried region 44a is
- the length of the buried region 44a is L, and one base diffusion region
- the number of the buried regions 44a located on the bottom of the 17a is n
- the region where the conductive region is formed is the region of the resistive layer 15 between the top of the buried region 44a (the bottom of the base diffusion region 17a) and the bottom.
- the base diffusion region 17a and the resistance layer 15 are reverse-biased, and the portion of the resistance layer 15 sandwiched between the buried regions 44a is filled with the depletion layer.
- the inside of the buried region 44a is also filled with the depletion layer (however, the electric field at the PN junction between the buried region 44a and the resistance layer 15 is reduced before the buried region 44a is filled with the depletion layer. It is assumed that the critical value that causes Avalanche yielding has not been reached.) 0
- FIG. 36 is a diagram for explaining a position where avalanche breakdown occurs, and is a position between the buried regions 44a connected to the same base diffusion region 17a and the depth of the bottom surface of the buried region 44a. (A), and a position shallower and closer to the base diffusion region 17a is indicated by (b).
- a position between the adjacent base diffusion regions 17a and near the depth of the bottom surface of the buried region 44a is indicated by a code (c), and a position shallower and closer to the base diffusion region 17a is a code (d) ).
- the center position force in the width direction of one base diffusion region 17a is used.
- the impurity amount of the first conductivity type is between H and H.
- Qd the case where Qd is large
- Qa of the second conductivity type is large.
- the resistance layer 15 has a high concentration, and between the base diffusion region 17a and the resistance layer 15 Resistance of pn junction Since the depletion layer hardly spreads in the layer 15, avalanche breakdown is likely to occur near the bottom surface of the base diffusion region 17a.
- the avalanche breakdown is likely to occur at the buried region 44a far and away.
- the avalanche breakdown occurs at a position (b) near the bottom surface of the base diffusion region 17a and near the bottom surface of the base diffusion region 17a, and the depth of the base diffusion region 17a between the base diffusion regions 17a. It is unlikely to occur at the position (d) close to the height. This has been confirmed by simulation.
- the parasitic bipolar transistor Since the avalanche current does not pass through the high-resistance portion below the bottom surface of the source diffusion region 21, the parasitic bipolar transistor does not turn on, and the breakdown is unlikely to occur.
- the depletion layer easily spreads in the resistance layer 15. In this case, avalanche breakdown is likely to occur at the depth and position (c) of the narrow portion between the embedded regions 44a.
- each variable in the above equation (2) is set to a value that substantially satisfies the equation (2), and is set to satisfy Wm> Wm. .
- Wm> Wm for example, it is set so that Wm ⁇ Wm X 2 is satisfied.
- Wm (5.25 ⁇ ) Wm 2 (5.25 Aim [0083] When Wm ⁇ Wm, when QdZQa ⁇ 1.25, avalanche breakdown occurs at position (d).
- each base diffusion region 17a Although two buried regions 44a are arranged below the bottom surface of each base diffusion region 17a in the above description, three or more buried regions 44a may be provided.
- the number of the buried regions 44a respectively located on the bottom surface of the 17a can be increased.
- the semiconductor material 40a grows on the inner surface of the groove 43a. Therefore, it is better to increase the number of the buried regions 44a.
- FIG. 1 (a) -FIG. 26 (a) is a cross-sectional view along the step of the active region where the base diffusion region 17a as described above is arranged
- FIG. 1 (b) —FIG. b) is a cross-sectional view of a part near the outer periphery of the active region and a breakdown voltage region surrounding the active region.
- Reference numeral 10 in FIGS. L (a) and (b) denotes a processing substrate for manufacturing the semiconductor device of the present invention.
- the processing substrate 10 has a semiconductor support layer 11 made of a semiconductor single crystal of the first conductivity type, and a semiconductor crystal of the same conductivity type as the semiconductor support layer 11 formed on the surface of the semiconductor support layer 11 by epitaxy. And a growth layer 12 formed as a film.
- An initial oxide film 28 made of a semiconductor single crystal oxide is formed on the surface of growth layer 12 by the thermal oxidation treatment.
- a resist film is formed on the surface of the processing substrate 10 and patterned, and a rectangular opening 49 is formed at a position on the active region of the resist film as shown in FIGS. 2 (a) and 2 (b).
- Reference numeral 41 in FIG. 2B indicates a patterned resist film, and an initial oxidation film 28 is exposed at the bottom of the opening 49.
- the initial oxidation film 28 located on the bottom surface of the opening 49 is removed by etching, the initial oxidation film 28 becomes a resist film 41 as shown in FIGS. 3 (a) and 3 (b).
- An opening 31 having the same shape as the opening 49 is formed. At the bottom of the opening 31, the surface of the growth layer 12 is exposed. (A), (b) In the state of ()), the resist film 41 has been removed.
- a relaxation layer made of a semiconductor oxide constituting the growth layer 12 is provided at the bottom of the opening 31. 32 are formed.
- the thickness of the relaxing layer 32 is formed thin.
- the impurity is shielded by the initial oxide film 28 and penetrates through the relaxation layer 32, and as shown in FIGS. 5 (a) and 5 (b).
- the first conductivity type high concentration impurity layer 13 is formed on the inner surface of the growth layer 12 at the bottom surface of the opening 31. The depth of the high-concentration impurity layer 13 is shallow.
- the impurities of the first conductivity type included in the high-concentration impurity layer 13 diffuse in the depth direction and the horizontal direction, and as shown in FIGS. 6 (a) and 6 (b). Then, a first conductive type conductive layer 14 is formed in the active region.
- the conductive layer 14 and the growth layer 12 form a first conductive type resistance layer 15.
- a thermal oxide film of a semiconductor is formed on the surface of the processing substrate 10 by thermal oxidation at the time of diffusion.
- Numeral 33 in FIGS. 6 (a) and 6 (b) indicates the thermal oxidation film and the mask oxidation film integrated with the relaxation layer 32 and the initial oxidation film 28.
- the concentration of the surface of the conductive layer 14 is higher by about one digit than that of the growth layer 12. Since the conductive layer 14 is formed by diffusion, its concentration becomes smaller as the surface becomes deeper and deeper. Since the conductive layer 14 and the growth layer 12 are of the same conductivity type and do not form a PN junction, in the present invention, the depth of the conductive layer 14 is defined at a position reduced to twice the concentration of the growth layer 12. Do
- FIG. 29 is a sectional view taken along line AA of FIGS. 6 (a) and 6 (b). Due to the lateral diffusion of the impurities of the first conductivity type, the planar shape of the conductive layer 14 is a quadrangle with four rounded corners larger than the high-concentration impurity layer 13.
- a resist film is formed on the mask oxide film 33 and patterned to form a plurality of parallel elongated openings 42a in the active region as shown in FIG. 7 (a). Also, as shown in FIG. 2B, a plurality of ring-shaped openings 42b are formed in the breakdown voltage region.
- Reference numeral 41 denotes a resist film in which openings 42a and 42b are formed.
- the elongated opening 42a is an elongated rectangle, and the ring-shaped opening 42b is a square ring having a different size. (A rectangular or square ring).
- the ring-shaped openings 42b are arranged concentrically, and the elongated openings 42a are surrounded by the respective ring-shaped openings 42b.
- Opposing sides of adjacent ring-shaped openings 42b are made parallel to each other, and four sides of the elongated openings 42a are made parallel or perpendicular to the sides of the ring-shaped openings 42b.
- the surface of the mask oxide film 33 is exposed at the bottom of each of the openings 42a and 42b, and the mask oxide film 33 at the bottom positions of the openings 42a and 42b is removed by etching.
- the resist film 41 is removed, and then the resistive layer 15 is etched by etching using the mask oxide film 33 as a mask, as shown in FIGS. 8 (a) and 8 (b).
- An active groove 43a is formed at the bottom of the elongated opening 42a, and a pressure-resistant groove 43b is formed at the bottom of the ring-shaped opening 42b.
- FIG. 30 is a sectional view taken along the line BB of FIGS. 8 (a) and 8 (b).
- the planar shape of the active groove 43a is an elongated rectangle like the elongated opening 42a, and the shape of the pressure-resistant groove 43b is the same square ring as the ring-shaped opening 42b.
- the depth of the active groove 43a and the withstand voltage groove 43b are the same, and are formed to be deeper than the conductive layer 14 and not to reach the semiconductor support layer 11. Therefore, the growth layer 12 is exposed at the bottom of each of the grooves 43a and 43b.
- the bottom surface of each groove 43a, 43b is parallel to the surface of the growth layer 12, and the side surface of each groove 43a, 43b is perpendicular to the bottom surface.
- a semiconductor single crystal or semiconductor polycrystal of the second conductivity type is grown on the bottom and side surfaces inside the trenches 43a and 43b by CVD, and as shown in FIGS. 9 (a) and 9 (b), The inside of each of the trenches 43a and 43b is filled with a second conductive type semiconductor material 40a made of a grown semiconductor single crystal or semiconductor polycrystal, and black.
- the mask oxide film 33 adhered to the growth layer 12 remains, and the surface of the resistance layer 15 in the breakdown voltage region (the growth layer 12), the surfaces of the conductive layer 14 in the active region and the surfaces of the semiconductor materials 40a and 40b in the active region and the breakdown voltage region are exposed.
- a thin gate insulating film 34 is formed by a thermal oxidation process, and then a conductive poly-Si is formed on the surface of the gate insulating film 34 by a CVD method or the like.
- a silicon thin film is deposited to form a conductive thin film 35 made of polysilicon.
- a patterned resist film 46 is arranged at a predetermined position on the conductive thin film 35, and the conductive thin film 35 is patterned by etching.
- a gate electrode film 36 is formed.
- the gate electrode film 36 and the mask oxide film 33 serve as a mask, and the impurities transmitted through the exposed gate insulating film 34
- the second conductive type high-concentration surface is formed on the inner surface of the conductive layer 14 and the inner surfaces of the semiconductor materials 40a and 40b inside the active groove 43a and the withstand voltage groove 43b. Impurity region 16 is formed.
- FIG. 17A and FIG. 17A A conductive base diffusion region 17a and an auxiliary guard diffusion region 17b are formed respectively.
- the base diffusion region 17a and the auxiliary guard diffusion region 17b have the same depth and are shallower than the depth of the conductive layer 14.
- the second conductive type buried region 44a is formed on the bottom surface of the base diffusion region 17a by the remaining portion (lower portion) of the active groove 43a and the semiconductor material 40a filled therein.
- the remaining portion (lower portion) of the pressure-resistant groove 43b and the inside thereof are filled.
- the second conductive type main guard region 44b is formed of the semiconductor material 40b.
- the buried region 44a is elongated and is parallel to each other.
- the buried region 44a is formed by a portion below the depth of the base diffusion region 17a, and has a horizontally-oriented rectangular parallelepiped shape. Further, since the upper portion of the buried region 44a is connected to the base diffusion region 17a, it has the same potential as the base diffusion region 17a.
- a high-concentration impurity region 16 having the same width as the semiconductor material 40b is formed above the semiconductor material 40b filled in the breakdown voltage groove 43b.
- the width of 7b is wider than the width of the main guard area 44b.
- FIG. 31 is a sectional view taken along line CC of FIGS. 17 (a) and (b).
- Each base diffusion region 17a is a rectangle whose four corners are rounded and whose long sides extend along the direction in which the buried region 44a extends.
- the base diffusion regions 17a are separated from each other, and the edge of the base diffusion region 17a enters below the bottom surface of the gate electrode film 36 due to the lateral diffusion of the impurity of the second conductivity type. 36 is located so as to straddle the adjacent base diffusion region 17a.
- the shape of the auxiliary guard diffusion region 17b is a square ring shape, and the auxiliary guard diffusion regions 17b concentrically adjacent to each other are separated from each other by a certain distance.
- a patterned resist film 45 is disposed on the surface of the processing substrate 10, and the gate insulating film 34 at the center in the width direction of the base diffusion region 17a is formed. Irradiation of impurities of the second conductivity type in the exposed state causes impurities of the second conductivity type that have passed through the gate insulating film 34 to cause a shallow surface on the inner surface of the base diffusion region 17a, resulting in high-concentration impurities of the second conductivity type.
- the second conductive type high-concentration impurity layer 18 has a long side that is a rectangle along the longitudinal direction of the base diffusion region 17a, and the long side of the high-concentration impurity layer 18 and the long side of the base diffusion region 17a. Are parallel.
- the long side of the high-concentration impurity layer 18 is separated from the edge of the gate electrode film 36 by a certain distance, and the resist film 45 is removed, as shown in FIGS. 19 (a) and (b). Then, another patterned resist film 46 was formed, and the surface of the gate insulating film 34 at a position between the long side of the high-concentration impurity layer 18 and the edge of the gate electrode film 36 was exposed to cover another portion. 1st conductivity type impurities in the state , The impurity penetrates through the exposed portion of the gate insulating film 34, and the first conductive film is formed on the inner surface of the base diffusion region 17a located between the high-concentration impurity region 18 of the second conductivity type and the gate electrode film 36. A high-concentration impurity region 19 is formed.
- the impurities contained in the high-concentration impurity regions 18 of the second conductivity type and the high-concentration impurity regions 19 of the first conductivity type are respectively diffused, and as shown in FIG.
- an ohmic diffusion region 20 of the second conductivity type and a source diffusion region 21 of the first conductivity type are formed, respectively.
- the surface concentration of the ohmic diffusion region 20 is higher than the surface concentration of the base diffusion region 17a, so that the source diffusion region 21 and the ohmic diffusion region 20 form an ohmic contact with the metal film.
- FIG. 32 shows a sectional view taken along line FF of FIGS. 20 (a) and (b).
- the planar shape of ohmic diffusion region 20 and source diffusion region 21 is smaller than base diffusion region 17a, and their depth is shallower than that of base diffusion region 17a.
- the ohmic diffusion region 20 and the source diffusion region 21 are located inside the base diffusion region 17a, and are not in contact with the conductive region 14 and the growth layer 12.
- At least one or more ohmic diffusion regions 20 and source diffusion regions 21 are formed in each base diffusion region 17a.
- the end of the source diffusion region 21 enters below the bottom of the gate electrode film 36 by lateral diffusion, but does not contact the end of the base diffusion region 17a, and
- the channel region 22 is formed by a portion of the base diffusion region 17a, which is in contact with the gate insulating film 34 between the edge of the source diffusion region 21 and the edge of the base diffusion region 17a.
- an interlayer insulating film 37 such as a silicon oxide film is formed on the surface of the processing substrate 10 by a CVD method or the like.
- a patterned resist film 47 is disposed on the gate electrode film 36 in the active region and on the surface of the breakdown voltage region, and the exposed interlayer insulating film 37 and the gate located thereunder are formed.
- the insulating film 34 is etched to expose at least a part of the surface of the ohmic diffusion region 20 and the source diffusion region 21. Then, as shown in FIGS. Then, the surface of the ohmic diffusion region 20-and the surface of the source diffusion region 21-come into contact with the metal thin film 29.
- a notched resist film (not shown) is arranged on the metal thin film 29 and etched.
- the source electrode film 38 is formed as shown in FIG.
- the source electrode film 38 When the source electrode film 38 is formed, the source electrode film 38 is formed of a metal film, is insulated from the source electrode film 38, and is connected to the gate pad connected to the gate electrode film 36 and the source electrode. A source pad that also forms part of the membrane 38 is formed.
- the source electrode film 38 is in ohmic contact with the source diffusion region 21 and the ohmic diffusion region 20, the source diffusion region 21 is directly electrically connected to the source electrode film 38, and the base diffusion region 17a is It is electrically connected to source electrode film 38 through diffusion region 20.
- the buried region 44a is in contact with the base diffusion region 17a, so that the buried region 44a is also electrically connected to the source electrode film 38.
- the source electrode film 38 is electrically insulated from the gate electrode film 36 by the interlayer insulating film 37, and does not contact the conductive layer 14 or the growth layer 12.
- a protection layer 39 made of a silicon oxide film or the like is formed on the surface of the processing substrate 10, and the protection layer 39 is patterned by etching. The patterning exposes the gate and source pads.
- a metal film is formed on the exposed surface on the back surface side of the semiconductor support layer 11, and the metal film forms the drain electrode film 30.
- a dicing step a plurality of semiconductor devices 1 are obtained from one wafer.
- the drain electrode film 30 is in ohmic contact with the semiconductor support layer 11, and the growth layer 12 and the conductive region 14 are electrically connected to the drain electrode film 30 via the semiconductor support layer 11.
- the above is the power when the semiconductor device 1 of the present invention is a MOS transistor.
- the present invention also includes other types of semiconductor devices.
- Reference numeral 2 in FIG. 33 denotes a PN junction type IGBT according to a second example of the present invention. This second
- the semiconductor device 2 of the second example has a collector layer 51 of the second conductivity type in place of the support layer 11 of the first conductivity type, and the first conductivity type is grown on the collector layer 51.
- Layer 12 is arranged.
- a collector electrode 55 On the back surface of the collector layer 51, a collector electrode 55 that is in ohmic contact with the collector layer 51 is formed.
- Other configurations are the same as those of the semiconductor device 1 of the first example.
- a PN junction is formed between the collector layer 51 and the growth layer 12, and when the semiconductor device 2 conducts, the PN junction is forward-biased and the power of the collector layer 51 also increases. Since the minority carriers are injected into the layer 12, the conduction resistance is reduced.
- Reference numeral 3 in FIG. 34 denotes a Schottky junction IGBT according to a third embodiment of the present invention.
- the surface of the growth layer 12 exposed by polishing is removed.
- a metal film such as chromium which forms a Schottky junction with the growth layer 12 is formed, and the Schottky electrode film 56 is formed by the metal film.
- the polarity of the Schottky junction is a polarity that is forward-biased when the semiconductor device 3 is turned on. Carriers are injected, and the conduction resistance decreases.
- Reference numeral 4 in FIG. 35 denotes a fourth example of the semiconductor device of the present invention, in which a first conductivity type growth layer 12 is formed on a second conductivity type support substrate 52 by epitaxy.
- the semiconductor device 4 has an isolation diffusion region 53 that is formed by diffusion from the surface of the resistance layer 15 and whose bottom surface reaches the semiconductor support layer 11.
- Separation diffusion region 53 has a ring shape and surrounds the active region in which base diffusion region 17a is arranged.
- the conductive region 14 is formed inside the region surrounded by the isolation diffusion region 53, and a drain of the first conductivity type formed simultaneously with the source diffusion region 21 is formed near the inner surface of the conductive region 14.
- a diffusion region 54 is provided.
- the source electrode film 3 is formed on the surface of the drain diffusion region 54.
- a drain electrode film 59 which is formed at the same time as 8 and is electrically insulated from the source electrode film 38, is provided, and these constitute the transistor 6.
- a semiconductor element 57 such as a small signal transistor or a diode is formed outside the ring-shaped separation / diffusion region 53, and a plurality of semiconductor elements 57 constitute an electronic circuit such as a control circuit. Being done.
- an earth electrode film 58 connected to the ground potential is formed on the surface of the support substrate 52.
- the gate electrode film 36 is connected to a semiconductor element 57 outside the isolation diffusion region 53, and the transistor 6 is controlled by a control circuit formed by the semiconductor element 57.
- the gate electrode film 36 When a voltage equal to or higher than the threshold voltage is applied to the gate electrode film 36 in a state where the ground electrode film 58 is set at the ground potential and a voltage is applied between the drain electrode film 59 and the source electrode film 38, the channel region An inversion layer is formed at 22 to conduct.
- the isolation diffusion region 53 and the resistance layer 15 are reverse-biased, and the transistor 6 and the other semiconductor element 57 are electrically isolated.
- a silicon single crystal can be used as the semiconductor single crystal, and a single crystal of another semiconductor such as GaAs can be used.
- each base diffusion region 17a is connected by a diffusion region of the second conductivity type to form a comb. Good.
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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EP04821017A EP1705715B1 (en) | 2004-01-07 | 2004-12-10 | Semiconductor device |
US11/481,247 US7282764B2 (en) | 2004-01-07 | 2006-07-06 | Semiconductor device |
HK07107130.9A HK1099847A1 (en) | 2004-01-07 | 2007-07-03 | Semiconductor device |
Applications Claiming Priority (2)
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JP2004001886A JP3681741B2 (ja) | 2004-01-07 | 2004-01-07 | 半導体装置 |
JP2004-001886 | 2004-01-07 |
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US11/481,247 Continuation US7282764B2 (en) | 2004-01-07 | 2006-07-06 | Semiconductor device |
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WO2005067057A1 true WO2005067057A1 (ja) | 2005-07-21 |
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PCT/JP2004/018480 WO2005067057A1 (ja) | 2004-01-07 | 2004-12-10 | 半導体装置 |
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US (1) | US7282764B2 (ja) |
EP (1) | EP1705715B1 (ja) |
JP (1) | JP3681741B2 (ja) |
KR (1) | KR100816702B1 (ja) |
CN (1) | CN100481501C (ja) |
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JP3681741B2 (ja) * | 2004-01-07 | 2005-08-10 | 新電元工業株式会社 | 半導体装置 |
JP6092680B2 (ja) * | 2013-03-26 | 2017-03-08 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
JP6092749B2 (ja) * | 2013-10-17 | 2017-03-08 | 新電元工業株式会社 | 半導体装置及び半導体装置の製造方法 |
CN108574012B (zh) * | 2017-03-08 | 2021-12-24 | 无锡华润华晶微电子有限公司 | 超结vdmos器件及其制备方法 |
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JP3636345B2 (ja) * | 2000-03-17 | 2005-04-06 | 富士電機デバイステクノロジー株式会社 | 半導体素子および半導体素子の製造方法 |
JP5134746B2 (ja) * | 2001-09-20 | 2013-01-30 | 新電元工業株式会社 | 電界効果トランジスタの製造方法 |
US6521954B1 (en) * | 2001-12-21 | 2003-02-18 | Kabushiki Kaisha Toshiba | Semiconductor device and manufacturing method thereof |
JP3681741B2 (ja) * | 2004-01-07 | 2005-08-10 | 新電元工業株式会社 | 半導体装置 |
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2004
- 2004-01-07 JP JP2004001886A patent/JP3681741B2/ja not_active Expired - Fee Related
- 2004-12-10 EP EP04821017A patent/EP1705715B1/en not_active Ceased
- 2004-12-10 WO PCT/JP2004/018480 patent/WO2005067057A1/ja not_active Application Discontinuation
- 2004-12-10 KR KR1020067013577A patent/KR100816702B1/ko not_active IP Right Cessation
- 2004-12-10 CN CNB2004800398545A patent/CN100481501C/zh not_active Expired - Fee Related
-
2006
- 2006-07-06 US US11/481,247 patent/US7282764B2/en not_active Expired - Fee Related
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2007
- 2007-07-03 HK HK07107130.9A patent/HK1099847A1/xx not_active IP Right Cessation
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Also Published As
Publication number | Publication date |
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EP1705715A1 (en) | 2006-09-27 |
EP1705715B1 (en) | 2012-08-22 |
CN1910758A (zh) | 2007-02-07 |
EP1705715A4 (en) | 2008-11-05 |
JP2005197439A (ja) | 2005-07-21 |
CN100481501C (zh) | 2009-04-22 |
KR100816702B1 (ko) | 2008-03-27 |
KR20060116017A (ko) | 2006-11-13 |
US7282764B2 (en) | 2007-10-16 |
US20070045776A1 (en) | 2007-03-01 |
JP3681741B2 (ja) | 2005-08-10 |
HK1099847A1 (en) | 2007-08-24 |
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