JP3680594B2 - 半導体集積回路 - Google Patents

半導体集積回路 Download PDF

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Publication number
JP3680594B2
JP3680594B2 JP31869298A JP31869298A JP3680594B2 JP 3680594 B2 JP3680594 B2 JP 3680594B2 JP 31869298 A JP31869298 A JP 31869298A JP 31869298 A JP31869298 A JP 31869298A JP 3680594 B2 JP3680594 B2 JP 3680594B2
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JP
Japan
Prior art keywords
node
circuit
source
gate
channel fet
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Expired - Fee Related
Application number
JP31869298A
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English (en)
Japanese (ja)
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JP2000151378A5 (enExample
JP2000151378A (ja
Inventor
一郎 河野
和男 矢野
直樹 加藤
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Hitachi Ltd
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Hitachi Ltd
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Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP31869298A priority Critical patent/JP3680594B2/ja
Priority to US09/436,501 priority patent/US6297674B1/en
Publication of JP2000151378A publication Critical patent/JP2000151378A/ja
Priority to US09/927,936 priority patent/US6515521B2/en
Publication of JP2000151378A5 publication Critical patent/JP2000151378A5/ja
Application granted granted Critical
Publication of JP3680594B2 publication Critical patent/JP3680594B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
JP31869298A 1998-11-10 1998-11-10 半導体集積回路 Expired - Fee Related JP3680594B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP31869298A JP3680594B2 (ja) 1998-11-10 1998-11-10 半導体集積回路
US09/436,501 US6297674B1 (en) 1998-11-10 1999-11-09 Semiconductor integrated circuit for low power and high speed operation
US09/927,936 US6515521B2 (en) 1998-11-10 2001-08-13 Semiconductor integrated circuit for low power and high speed operation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31869298A JP3680594B2 (ja) 1998-11-10 1998-11-10 半導体集積回路

Publications (3)

Publication Number Publication Date
JP2000151378A JP2000151378A (ja) 2000-05-30
JP2000151378A5 JP2000151378A5 (enExample) 2004-09-30
JP3680594B2 true JP3680594B2 (ja) 2005-08-10

Family

ID=18101957

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31869298A Expired - Fee Related JP3680594B2 (ja) 1998-11-10 1998-11-10 半導体集積回路

Country Status (2)

Country Link
US (2) US6297674B1 (enExample)
JP (1) JP3680594B2 (enExample)

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DE19934297C1 (de) * 1999-07-21 2000-10-05 Siemens Ag Integrierte Halbleiterschaltung mit erhöhter Betriebsspannung für programmierbare Elemente (z.B. zur Konfigurierung)
JP2002064150A (ja) * 2000-06-05 2002-02-28 Mitsubishi Electric Corp 半導体装置
JP4366858B2 (ja) * 2000-09-18 2009-11-18 ソニー株式会社 Ｍｏｓトランジスタ回路
US7295457B2 (en) * 2002-11-29 2007-11-13 International Business Machines Corporation Integrated circuit chip with improved array stability
US6798682B2 (en) * 2002-11-29 2004-09-28 International Business Machines Corp. Reduced integrated circuit chip leakage and method of reducing leakage
US7084476B2 (en) * 2004-02-26 2006-08-01 International Business Machines Corp. Integrated circuit logic with self compensating block delays
US7327598B2 (en) * 2004-11-10 2008-02-05 Texas Instruments Incorporated High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode
US7230463B2 (en) * 2005-03-30 2007-06-12 International Business Machines Corporation Method and apparatus for controlling transition rates on adjacent interconnects
WO2006137114A1 (ja) * 2005-06-20 2006-12-28 Fujitsu Limited セレクタ回路及び回路接続方法
US7292061B2 (en) * 2005-09-30 2007-11-06 Masaid Technologies Incorporated Semiconductor integrated circuit having current leakage reduction scheme
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US7908578B2 (en) 2007-08-02 2011-03-15 Tela Innovations, Inc. Methods for designing semiconductor device with dynamic array section
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US7619916B2 (en) * 2006-07-06 2009-11-17 Stmicroelectronics Pvt. Ltd. 8-T SRAM cell circuit, system and method for low leakage current
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US7659768B2 (en) * 2007-12-28 2010-02-09 Advanced Micro Devices, Inc. Reduced leakage voltage level shifting circuit
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
KR101739709B1 (ko) 2008-07-16 2017-05-24 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8464199B1 (en) * 2012-05-16 2013-06-11 International Business Machines Corporation Circuit design using design variable function slope sensitivity
US9678154B2 (en) 2014-10-30 2017-06-13 Qualcomm Incorporated Circuit techniques for efficient scan hold path design

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0289292A (ja) * 1988-09-26 1990-03-29 Toshiba Corp 半導体メモリ
JPH04130770A (ja) * 1990-09-21 1992-05-01 Mitsubishi Electric Corp 半導体集積回路
US5331228A (en) * 1992-07-31 1994-07-19 Sgs-Thomson Microelectronics, Inc. Output driver circuit
US5585740A (en) * 1993-12-10 1996-12-17 Ncr Corporation CMOS low output voltage bus driver with controlled clamps
JP3195146B2 (ja) 1993-12-13 2001-08-06 株式会社東芝 半導体集積回路
US5440258A (en) * 1994-02-08 1995-08-08 International Business Machines Corporation Off-chip driver with voltage regulated predrive
KR0179786B1 (ko) * 1995-12-23 1999-04-01 문정환 출력버퍼
US5801563A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Output driver circuitry having a single slew rate resistor
US5894238A (en) * 1997-01-28 1999-04-13 Chien; Pien Output buffer with static and transient pull-up and pull-down drivers
JP3723317B2 (ja) * 1997-04-08 2005-12-07 株式会社アドバンテスト 信号伝送に用いる駆動回路、バイアス発生回路
JP3123463B2 (ja) * 1997-05-16 2001-01-09 日本電気株式会社 レベル変換回路
US5917348A (en) * 1997-09-02 1999-06-29 Industrial Technology Research Institute--Computer & Communication Research Labs. CMOS bidirectional buffer for mixed voltage applications
JP2000295094A (ja) * 1999-04-07 2000-10-20 Mitsubishi Electric Corp バッファ回路およびそれを用いた電位検出回路

Also Published As

Publication number Publication date
US6515521B2 (en) 2003-02-04
US6297674B1 (en) 2001-10-02
JP2000151378A (ja) 2000-05-30
US20020030510A1 (en) 2002-03-14

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