JP3648053B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP3648053B2
JP3648053B2 JP12130598A JP12130598A JP3648053B2 JP 3648053 B2 JP3648053 B2 JP 3648053B2 JP 12130598 A JP12130598 A JP 12130598A JP 12130598 A JP12130598 A JP 12130598A JP 3648053 B2 JP3648053 B2 JP 3648053B2
Authority
JP
Japan
Prior art keywords
semiconductor chip
substrate
resin
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12130598A
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English (en)
Japanese (ja)
Other versions
JPH11312712A (ja
JPH11312712A5 (https=
Inventor
良実 江川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP12130598A priority Critical patent/JP3648053B2/ja
Priority to US09/177,822 priority patent/US6229215B1/en
Publication of JPH11312712A publication Critical patent/JPH11312712A/ja
Publication of JPH11312712A5 publication Critical patent/JPH11312712A5/ja
Application granted granted Critical
Publication of JP3648053B2 publication Critical patent/JP3648053B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/012—Manufacture or treatment of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP12130598A 1998-04-30 1998-04-30 半導体装置 Expired - Fee Related JP3648053B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP12130598A JP3648053B2 (ja) 1998-04-30 1998-04-30 半導体装置
US09/177,822 US6229215B1 (en) 1998-04-30 1998-10-23 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12130598A JP3648053B2 (ja) 1998-04-30 1998-04-30 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2003306721A Division JP3648238B2 (ja) 2003-08-29 2003-08-29 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JPH11312712A JPH11312712A (ja) 1999-11-09
JPH11312712A5 JPH11312712A5 (https=) 2004-09-09
JP3648053B2 true JP3648053B2 (ja) 2005-05-18

Family

ID=14807972

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12130598A Expired - Fee Related JP3648053B2 (ja) 1998-04-30 1998-04-30 半導体装置

Country Status (2)

Country Link
US (1) US6229215B1 (https=)
JP (1) JP3648053B2 (https=)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
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JP2000260912A (ja) * 1999-03-05 2000-09-22 Fujitsu Ltd 半導体装置の実装構造及び半導体装置の実装方法
JP2000340736A (ja) * 1999-05-26 2000-12-08 Sony Corp 半導体装置及びその実装構造、並びにこれらの製造方法
US6232667B1 (en) * 1999-06-29 2001-05-15 International Business Machines Corporation Technique for underfilling stacked chips on a cavity MLC module
JP3526788B2 (ja) 1999-07-01 2004-05-17 沖電気工業株式会社 半導体装置の製造方法
JP2001044358A (ja) * 1999-07-28 2001-02-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
TW417839U (en) * 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
SG83742A1 (en) * 1999-08-17 2001-10-16 Micron Technology Inc Multi-chip module with extension
CN1199269C (zh) 1999-10-01 2005-04-27 精工爱普生株式会社 半导体装置及其制造方法和制造装置
JP3485507B2 (ja) * 1999-10-25 2004-01-13 沖電気工業株式会社 半導体装置
US6369448B1 (en) * 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6437990B1 (en) * 2000-03-20 2002-08-20 Agere Systems Guardian Corp. Multi-chip ball grid array IC packages
CN1207785C (zh) 2000-03-21 2005-06-22 三菱电机株式会社 半导体器件、电子装置的制造方法、电子装置和携带式信息终端
JP3581086B2 (ja) * 2000-09-07 2004-10-27 松下電器産業株式会社 半導体装置
US6749691B2 (en) 2001-02-14 2004-06-15 Air Liquide America, L.P. Methods of cleaning discolored metallic arrays using chemical compositions
US8143108B2 (en) 2004-10-07 2012-03-27 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
USRE44438E1 (en) 2001-02-27 2013-08-13 Stats Chippac, Ltd. Semiconductor device and method of dissipating heat from thin package-on-package mounted to substrate
US20020121707A1 (en) * 2001-02-27 2002-09-05 Chippac, Inc. Super-thin high speed flip chip package
SG108245A1 (en) * 2001-03-30 2005-01-28 Micron Technology Inc Ball grid array interposer, packages and methods
SG122743A1 (en) * 2001-08-21 2006-06-29 Micron Technology Inc Microelectronic devices and methods of manufacture
US6519844B1 (en) * 2001-08-27 2003-02-18 Lsi Logic Corporation Overmold integrated circuit package
US6963142B2 (en) * 2001-10-26 2005-11-08 Micron Technology, Inc. Flip chip integrated package mount support
US7573136B2 (en) * 2002-06-27 2009-08-11 Micron Technology, Inc. Semiconductor device assemblies and packages including multiple semiconductor device components
JP4110992B2 (ja) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
US7262507B2 (en) * 2003-12-26 2007-08-28 Nec Electronics Corporation Semiconductor-mounted device and method for producing same
JP4865197B2 (ja) 2004-06-30 2012-02-01 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
DE102004042563A1 (de) * 2004-09-02 2006-03-23 Infineon Technologies Ag Halbleiter-Bauelement mit verbesserter Wärmeableitung
JP2006190746A (ja) * 2005-01-05 2006-07-20 Seiko Epson Corp 半導体装置及びその製造方法
WO2006090827A1 (ja) * 2005-02-25 2006-08-31 Kyocera Corporation 電子装置及びその製造方法
JP4575205B2 (ja) * 2005-03-30 2010-11-04 Ｏｋｉセミコンダクタ株式会社 積層構造体の形成方法及びその方法を使用した半導体装置の製造方法
JP2006310649A (ja) * 2005-04-28 2006-11-09 Sharp Corp 半導体装置パッケージおよびその製造方法、ならびに半導体装置パッケージ用一括回路基板
US7791192B1 (en) * 2006-01-27 2010-09-07 Xilinx, Inc. Circuit for and method of implementing a capacitor in an integrated circuit
JP2009088226A (ja) * 2007-09-28 2009-04-23 Seiko Epson Corp デバイス、デバイスの製造方法及び電子機器
WO2009057259A1 (ja) * 2007-11-01 2009-05-07 Panasonic Corporation 電子部品実装構造体およびその製造方法
US8110908B2 (en) * 2008-12-04 2012-02-07 Stats Chippac Ltd. Integrated circuit packaging system using bottom flip chip die bonding and method of manufacture thereof
CN101840894B (zh) * 2009-03-19 2012-04-04 松下电器产业株式会社 半导体器件
US8119447B2 (en) * 2009-06-17 2012-02-21 Stats Chippac Ltd. Integrated circuit packaging system with through via die having pedestal and recess and method of manufacture thereof
US8624364B2 (en) * 2010-02-26 2014-01-07 Stats Chippac Ltd. Integrated circuit packaging system with encapsulation connector and method of manufacture thereof
US8304880B2 (en) 2010-09-14 2012-11-06 Stats Chippac Ltd. Integrated circuit packaging system with package-on-package and method of manufacture thereof
US20120091575A1 (en) * 2010-10-15 2012-04-19 Yi-Shao Lai Semiconductor Package And Method For Making The Same
US8927391B2 (en) * 2011-05-27 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package process for applying molding compound
JP2013069942A (ja) * 2011-09-24 2013-04-18 Denso Corp 半導体装置及びその製造方法
US20190104610A1 (en) * 2017-09-29 2019-04-04 Intel Corporation Substrate architecture for solder joint reliabilty in microelectronic package structures and methods of forming the same
US11469216B2 (en) * 2020-03-27 2022-10-11 Nanya Technology Corporation Dual-die semiconductor package and manufacturing method thereof
KR102948469B1 (ko) 2021-06-25 2026-04-06 삼성전자주식회사 반도체 패키지

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US5200362A (en) * 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US5477082A (en) * 1994-01-11 1995-12-19 Exponential Technology, Inc. Bi-planar multi-chip module
JP2531382B2 (ja) 1994-05-26 1996-09-04 日本電気株式会社 ボ―ルグリッドアレイ半導体装置およびその製造方法
JPH08139225A (ja) 1994-11-11 1996-05-31 Hitachi Chem Co Ltd 半導体パッケージおよびその製造方法
EP0732107A3 (en) * 1995-03-16 1997-05-07 Toshiba Kk Shielding device for a circuit substrate
JPH0951015A (ja) 1995-08-09 1997-02-18 Citizen Watch Co Ltd 半導体装置
US5798567A (en) * 1997-08-21 1998-08-25 Hewlett-Packard Company Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors
US5854507A (en) * 1998-07-21 1998-12-29 Hewlett-Packard Company Multiple chip assembly

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Publication number Publication date
JPH11312712A (ja) 1999-11-09
US6229215B1 (en) 2001-05-08

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