JP3330605B2 - Ｄｒａｍセル用メモリコンデンサの製造方法 - Google Patents

Ｄｒａｍセル用メモリコンデンサの製造方法

Info

Publication number
JP3330605B2
JP3330605B2 JP50280694A JP50280694A JP3330605B2 JP 3330605 B2 JP3330605 B2 JP 3330605B2 JP 50280694 A JP50280694 A JP 50280694A JP 50280694 A JP50280694 A JP 50280694A JP 3330605 B2 JP3330605 B2 JP 3330605B2
Authority
JP
Japan
Prior art keywords
film
sio
auxiliary film
auxiliary
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP50280694A
Other languages
English (en)
Japanese (ja)
Other versions
JPH07509346A (ja
Inventor
レースナー、ウオルフガング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of JPH07509346A publication Critical patent/JPH07509346A/ja
Application granted granted Critical
Publication of JP3330605B2 publication Critical patent/JP3330605B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/041—Manufacture or treatment of capacitors having no potential barriers
    • H10D1/042—Manufacture or treatment of capacitors having no potential barriers using deposition processes to form electrode extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/716—Electrodes having non-planar surfaces, e.g. formed by texturisation having vertical extensions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP50280694A 1992-07-08 1993-06-15 Ｄｒａｍセル用メモリコンデンサの製造方法 Expired - Fee Related JP3330605B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4222467A DE4222467C1 (cg-RX-API-DMAC10.html) 1992-07-08 1992-07-08
DE4222467.5 1992-07-08
PCT/DE1993/000516 WO1994001891A1 (de) 1992-07-08 1993-06-15 Verfahren zur herstellung von speicherkondensatoren für dram-zellen

Publications (2)

Publication Number Publication Date
JPH07509346A JPH07509346A (ja) 1995-10-12
JP3330605B2 true JP3330605B2 (ja) 2002-09-30

Family

ID=6462779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50280694A Expired - Fee Related JP3330605B2 (ja) 1992-07-08 1993-06-15 Ｄｒａｍセル用メモリコンデンサの製造方法

Country Status (9)

Country Link
US (1) US5496757A (cg-RX-API-DMAC10.html)
EP (1) EP0649566B1 (cg-RX-API-DMAC10.html)
JP (1) JP3330605B2 (cg-RX-API-DMAC10.html)
KR (1) KR100309614B1 (cg-RX-API-DMAC10.html)
AT (1) ATE160652T1 (cg-RX-API-DMAC10.html)
DE (2) DE4222467C1 (cg-RX-API-DMAC10.html)
HK (1) HK1002337A1 (cg-RX-API-DMAC10.html)
TW (1) TW358242B (cg-RX-API-DMAC10.html)
WO (1) WO1994001891A1 (cg-RX-API-DMAC10.html)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19640273C1 (de) 1996-09-30 1998-03-12 Siemens Ag Verfahren zur Herstellung barrierenfreier Halbleiterspeicheranordnungen
US6395613B1 (en) * 2000-08-30 2002-05-28 Micron Technology, Inc. Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts
US5998256A (en) 1996-11-01 1999-12-07 Micron Technology, Inc. Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry
KR100227070B1 (ko) * 1996-11-04 1999-10-15 구본준 커패시터 및 그의 제조방법
US6590250B2 (en) 1997-11-25 2003-07-08 Micron Technology, Inc. DRAM capacitor array and integrated device array of substantially identically shaped devices
JP2000077619A (ja) * 1998-08-27 2000-03-14 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
US6157067A (en) * 1999-01-04 2000-12-05 International Business Machines Corporation Metal oxide semiconductor capacitor utilizing dummy lithographic patterns
KR100338959B1 (ko) * 2000-08-31 2002-06-01 박종섭 반도체 소자의 커패시터 하부전극 제조방법
KR100502410B1 (ko) * 2002-07-08 2005-07-19 삼성전자주식회사 디램 셀들
US7468323B2 (en) * 2004-02-27 2008-12-23 Micron Technology, Inc. Method of forming high aspect ratio structures

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62286270A (ja) * 1986-06-05 1987-12-12 Sony Corp 半導体メモリ装置
IT1245495B (it) * 1990-01-26 1994-09-27 Mitsubishi Electric Corp Memoria ad accesso casuale dinamica avente un condensatore del tipo impilato e procedimento di fabbricazione di essa
DD299990A5 (de) * 1990-02-23 1992-05-14 Dresden Forschzentr Mikroelek Ein-Transistor-Speicherzellenanordnung und Verfahren zu deren Herstellung
JP2519569B2 (ja) * 1990-04-27 1996-07-31 三菱電機株式会社 半導体記憶装置およびその製造方法
JPH0629483A (ja) * 1991-04-29 1994-02-04 Micron Technol Inc スタック型ｉセルキャパシタおよびその製造方法

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Ｔ．Ｋａｇａ ｅｔ ａｌ．，"Ｃｒｏｗｎ−Ｓｈａｐｅｄ Ｓｒａｃｋｅｄ−Ｃａｐａｃｉｔｏｒ Ｃｅｌｌ ｆｏｒ １．５−Ｖ Ｏｐｅｒａｔｉｏｎ ６４−Ｍｂ ＤＲＡＭ’ｓ"，ＩＥＥＥ ＴＲＡＭＳＡＣＴＩＯＮＳ ＯＮ ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥＳ，米国，ＩＥＥＥ，１９９１年 ２月，Ｖｏｌ．３８，Ｎｏ．２，ｐｐ．２５５−２６１
Ｗ．Ｗａｋａｍｉｙａ ｅｔ ａｌ．，"Ｎｏｖｅｌ Ｓｔａｃｋｅｄ Ｃａｐａｃｉｔｏｒ Ｃｅｌｌ ｆｏｒ ６４Ｍｂ ＤＲＡＭ"，１９８９ ＳＹＭＰＯＳＩＵＭ ＯＮ ＶＬＳＩ ＴＥＣＨＮＯＬＯＧＹ，米国，ＩＥＥＥ，１９８９年 ５月，ｐｐ．６９−７０
Ｙ．Ｋａｗａｍｏｔｏ ｅｔ ａｌ．，"Ａ １．２８μｍ２ Ｂｉｔ−Ｌｉｎｅ Ｓｈｉｅｌｄｅｄ Ｍｅｍｏｒｙ Ｃｅｌｌ Ｔｅｃｈｎｏｌｏｇｙ ｆｏｒ ６４Ｍｂ ＤＲＡＭｓ"，１９９０ ＳＹＭＰＯＳＩＵＭ ＯＮ ＶＬＳＩ ＴＥＣＨＮＯＬＯＧＹ，米国，ＩＥＥＥ，１９９０年 １月，ｐｐ．１３−１４

Also Published As

Publication number Publication date
KR950702748A (ko) 1995-07-29
HK1002337A1 (en) 1998-08-14
JPH07509346A (ja) 1995-10-12
EP0649566A1 (de) 1995-04-26
WO1994001891A1 (de) 1994-01-20
KR100309614B1 (ko) 2002-08-27
DE4222467C1 (cg-RX-API-DMAC10.html) 1993-06-24
US5496757A (en) 1996-03-05
DE59307748D1 (de) 1998-01-08
TW358242B (en) 1999-05-11
ATE160652T1 (de) 1997-12-15
EP0649566B1 (de) 1997-11-26

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