JP2986081B2 - シリコン技術における高価なメタライゼーションを使用しない高qインダクタ構造 - Google Patents
シリコン技術における高価なメタライゼーションを使用しない高qインダクタ構造Info
- Publication number
- JP2986081B2 JP2986081B2 JP7228714A JP22871495A JP2986081B2 JP 2986081 B2 JP2986081 B2 JP 2986081B2 JP 7228714 A JP7228714 A JP 7228714A JP 22871495 A JP22871495 A JP 22871495A JP 2986081 B2 JP2986081 B2 JP 2986081B2
- Authority
- JP
- Japan
- Prior art keywords
- metal
- inductor structure
- inductor
- stage
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims description 13
- 229910052710 silicon Inorganic materials 0.000 title claims description 13
- 239000010703 silicon Substances 0.000 title claims description 13
- 238000005516 engineering process Methods 0.000 title claims description 11
- 238000001465 metallisation Methods 0.000 title description 3
- 239000002184 metal Substances 0.000 claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000004804 winding Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Coils Or Transformers For Communication (AREA)
Description
クタの設計および構造に関し、詳細には、低コストのシ
リコン技術に適合する新規のモノリシック・インダクタ
構造に関する。
の小型化を達成するのみならず、回路の製造コストを減
らすためにも、実質上あらゆる分野で目標とされてい
る。複雑なマイクロプロセッサおよび演算増幅器を含め
て、多くのディジタル回路およびアナログ回路は、シリ
コン・ベースの集積回路(IC)として実施され成功を
収めてきた。このような回路は通常、バイポーラ・トラ
ンジスタ、電界効果トランジスタ(FET)、様々なタ
イプのダイオードなどの能動素子、およびレジスタやコ
ンデンサなどの受動素子が含まれる。
は、セルラ電話、無線モデム、および他のタイプの通信
装置に使用されるような、無線周波数(RF)回路があ
る。問題は、RF応用例に適した良質のインダクタをシ
リコン技術で製造するのが困難なことである。インダク
タをシリコン技術に組み込むことが試みられたが、イン
ダクタのQ値が5未満になったり、あるいは金のような
特別なメタライゼーション層が必要であった。
の直流(DC)抵抗が、インダクタQ値の低下の主な原
因になっていることは周知である。この効果を減少させ
る1つの方法は、幅の広い金属線を使用することである
が、そうするとインダクタ面積が増大し構造に関連する
寄生キャパシタンスが増加してしまう。インダクタ面積
が増大すると、達成可能な小型化が制限され、大きな面
積に関連する寄生キャパシタンスがインダクタの自己共
振周波数を減少させ、このため、その有効周波数が制限
される。さらに、Q値は、周波数に正比例し、インダク
タの直列損失に反比例するので、むやみに大きな金属線
幅を選ぶことはできない。
目的は、シリコン技術による新規のモノリシック高Qイ
ンダクタ構造を提供することである。
集積回路技術で複数のメタライゼーション段を設けて形
成され、インダクタの巻線にこれらの段を利用してイン
ダクタの抵抗を下げる、高Qのインダクタが提供され
る。この手法により、Q値が5より大きいインダクタ
を、無線周波数およびマイクロ波周波数においてこの手
法で組み込むことができる。
は、図面を参照した本発明の好ましい実施例の詳細な説
明によってよりよく理解されるであろう。
発明の好ましい実施例によるスパイラル・インダクタ構
造の平面図が示されている。図2および図3に示すよう
に、この構造は、3つの金属段から成り、第1金属段1
は、シリコン基板3上の二酸化シリコン層2の上の段で
ある。図3を参照のこと。第1金属段1は、第2二酸化
シリコン層4で覆われ、層4を貫いてバイア5が形成さ
れている。第1金属段1は、スパイラル構造の中心端子
6(図1)に接続するための下部交差線として使われ
る。バイア5には、金属が充填され、第1金属段と第2
金属段7とを相互接続するようになっている。この第2
段7は、第3二酸化シリコン層8で覆われ、その内部に
複数のバイア9が形成されている。図2に示すように、
バイア9には、金属が充填され、第2金属段7と第3金
属段10とを相互接続するようになっている。図1およ
び図3に示すように、2つの金属段7および10は同一
のスパイラル金属パターンであり、バイア9が2つの金
属段を効果的に分流する。したがって、2つの層がイン
ダクタの巻線に使われ、これらの2つの層は、直流抵抗
を減少させるために並列に接続された2つのインダクタ
をもたらす。2層インダクタの直流抵抗の減少は少なく
とも1/2であり、それゆえ大きなQ値の増大をもたら
す。追加の配線段が本技術によって提供されるなら、よ
り多くの金属層を分流することにより、直流抵抗をさら
に減少させることができることは明らかである。
れた複数の金属層を用いることにより、この手法は、高
周波数(ギガ・ヘルツ領域に達する)応用例用のインダ
クタ設計の問題を解決する。現在のほとんどのシリコン
技術には、回路配線用の少なくとも3層あるいはそれ以
上の金属層がある。第1金属段は、図1に示すように、
スパイラル構造の回路端子に接続するため下部交差線と
して使用され、したがって少なくとも2層がインダクタ
の巻線用に残されている。本発明は、成熟したBiCM
OS(バイポーラ相補型金属酸化膜半導体)技術を使用
するハードウェアとして実施された。
ンダクタで測定したQ値は、2.4GHzで少なくとも
7であった。このインダクタは、2つの金属段を使用し
て巻線を実施し、第3の段を下部交差線用に使用する。
このインダクタは、図4に示すように、2.4GHzの
コルピッツ・バイポーラ発振器の共振器の一部として良
好に機能した。
説明したが、当業者には、本発明が冒頭の特許請求の範
囲の趣旨および範囲に含まれる変更を加えて実施できる
ことが理解されよう。
の事項を開示する。
縁層により互いに分離された少なくとも第2と第3の金
属段を備える高Qモノリシック・インダクタ構造であっ
て、前記第2および第3金属段が同一のスパイラル・パ
ターンで形成され、低い抵抗値を有するインダクタ構造
の並列接続巻線を実施するように前記第3絶縁層を貫通
するバイア・ホールを介して接続されている、インダク
タ構造。 (2)シリコン基板を覆う第1絶縁層上に形成された第
1金属段をさらに備え、前記第1金属段が、前記第2お
よび第3金属段のスパイラル・パターンの下を交差し
て、インダクタ構造の第1端子に接続されるパターンを
有し、前記第2および第3金属段の一方が、インダクタ
構造の第2端子に接続され、前記第2金属段が、第2絶
縁層によって前記第1金属段から分離され、前記第2絶
縁層を貫通するバイア・ホールによって前記スパイラル
・パターンの中心部で前記第1金属段に接続されてい
る、請求項1に記載のインダクタ構造。 (3)前記第1、第2および第3絶縁層が二酸化シリコ
ンである、請求項2に記載のインダクタ構造。 (4)前記インダクタ構造が2.4〜2.5GHzの帯
域で7以上のQ値を有する、請求項3に記載のインダク
タ構造。
ル・インダクタ構造の上面図である。
れる下部交差設計を示すインダクタの断面図である。
タを使用する発振器の周波数スペクトルを示すグラフで
ある。
Claims (4)
- 【請求項1】通常のシリコン技術を使用して形成され、
第3絶縁層により互いに分離された少なくとも第2と第
3の金属段を備える高Qモノリシック・インダクタ構造
であって、前記第2および第3金属段が同一のスパイラ
ル・パターンで形成され、低い抵抗値を有するインダク
タ構造の並列接続巻線を実施するように前記第3絶縁層
を貫通するバイア・ホールを介して接続されている、イ
ンダクタ構造。 - 【請求項2】シリコン基板を覆う第1絶縁層上に形成さ
れた第1金属段をさらに備え、前記第1金属段が、前記
第2および第3金属段のスパイラル・パターンの下を交
差して、インダクタ構造の第1端子に接続されるパター
ンを有し、前記第2および第3金属段の一方が、インダ
クタ構造の第2端子に接続され、前記第2金属段が、第
2絶縁層によって前記第1金属段から分離され、前記第
2絶縁層を貫通するバイア・ホールによって前記スパイ
ラル・パターンの中心部で前記第1金属段に接続されて
いる、請求項1に記載のインダクタ構造。 - 【請求項3】前記第1、第2および第3絶縁層が二酸化
シリコンである、請求項2に記載のインダクタ構造。 - 【請求項4】前記インダクタ構造が2.4〜2.5GH
zの帯域で7以上のQ値を有する、請求項3に記載のイ
ンダクタ構造。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US307953 | 1994-09-16 | ||
US08/307,953 US5446311A (en) | 1994-09-16 | 1994-09-16 | High-Q inductors in silicon technology without expensive metalization |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0897377A JPH0897377A (ja) | 1996-04-12 |
JP2986081B2 true JP2986081B2 (ja) | 1999-12-06 |
Family
ID=23191883
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7228714A Expired - Lifetime JP2986081B2 (ja) | 1994-09-16 | 1995-09-06 | シリコン技術における高価なメタライゼーションを使用しない高qインダクタ構造 |
Country Status (2)
Country | Link |
---|---|
US (1) | US5446311A (ja) |
JP (1) | JP2986081B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20140124851A (ko) * | 2012-02-20 | 2014-10-27 | 후아웨이 테크놀러지 컴퍼니 리미티드 | 전력 전송 애플리케이션을 위한 고 전류, 저 등가 직렬 저항의 인쇄 회로 기판 코일 |
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