CN104269375B - 一种立体集成电感电容结构的制备方法 - Google Patents
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Abstract
本发明涉及半导体制造技术领域,尤其涉及一种立体集成电感电容结构的制备方法,可以实现三维立体结构的电感电容,通过制备顶部金属导线与底部金属导线互联形成以磁芯为中心单方向绕行的立体螺旋状的电感线圈,可以在相对较小的空间中同时获取电容电感,降低了电容电感的制作成本,同时也极大的提高了电感磁通量以增加电感值并降低涡旋电流,并提高品质因数Q值以及电感线圈的性能。
Description
技术领域
本发明涉及半导体制造技术领域,尤其涉及一种立体集成电感电容结构的制备方法。
背景技术
随着科学技术的进步以及社会信息化程度的提高,计算机、通讯等越来越多的技术领域均采用射频技术,促进了射频技术(RFIC)的高速发展,对于高频率、小功耗、低失真的射频技术的要求,使得电感线圈成为必要,电感线圈是由导线绕制在导线框架上,导线彼此相互绝缘,而绕制可以是空心的也可以是包含铁芯,简称电感,电感主要用于对交流信号进行隔离、滤波或者与电容、电阻组成谐振回路。而评价电感性能最重要的指标为品质因数Q(quality),品质因数Q(即Q值)表示一个储能器件(如电感线圈、电容等)、谐振电路中所储能量同每周期损耗能量之比,因此提高电感的品质因数Q可以提高集成电感的性能指标。
现有技术中大多数采用平面结构的集成电感,由于这种集成电感制作于衬底平行的平面上,在高频条件下,衬底中会形成涡旋电流(Eddy Current),而涡旋电流的方向与电感线圈中的电流方向相反,这必然会导致电感线圈的磁通量减少,额外的能量损失较大并使得整个电感的Q值下降。另外现有技术中,集成电感由于集成电路的制程与材料的限制,很难同时达到高电感值和高品质因数Q值,而且同时具有电感和电容的电路结构需要增大器件的面积,一定程度上增加了制作成本。
现有技术中以减少衬底的损耗入手来解决衬底中涡旋电流的问题,但是采用的均是平面结构的集成电感,受到平面电感工作原理的限制无法从根本上解决问题,无法提高电感磁通量以增加电感值的同时降低涡旋电流并提高品质因数Q值,因此发明一种高性能的集成电感和电容器件成为半导体制造技术领域的一个难题。
发明内容
鉴于上述问题,本发明提供一种立体集成电感电容结构的制备方法,以解决制备成本较高且无法提高电感磁通量以增加电感值的同时降低涡旋电流并提高品质因数Q值的缺陷。
本发明解决上述技术问题所采用的技术方案为:
一种立体集成电感电容结构的制备方法,其中,所述方法包括:
步骤S1、提供一半导体衬底,并于所述半导体衬底之上依次制备第一绝缘层和底层金属薄膜,并去除部分所述底层金属薄膜,以于所述第一绝缘层之上形成若干平行排列的底部金属导线;
步骤S2、制备第二绝缘层覆盖所述底部金属导线及所述第一绝缘层暴露的表面,并刻蚀所述第二绝缘层,以于各所述底部金属导线的长度延伸方向的两端端部区域之上均形成一第一通孔;
于所述第一通孔中填充第一金属,以于所述底部金属导线之上形成两列第一金属孔连线;
步骤S3、制备第三绝缘层覆盖所述第一金属孔连线和所述第二绝缘层的上表面,并刻蚀第三绝缘层,以于各所述第一金属孔连线之上形成一第二通孔及若干环状凹槽,且各第二通孔均环绕设置有至少两个所述环状凹槽;
于所述第二通孔和所述环状凹槽中填充第二金属,以于各所述第一金属孔连线之上均形成第二金属孔连线和若干环状的磁芯;
步骤S4、制备第四绝缘层覆盖所述第二金属孔连线、所述磁芯和所述第三绝缘层的上表面,并刻蚀第四绝缘层,以于各所述第二金属孔连线之上均形成一第三通孔和位于各磁芯之上的一第四通孔;
于所述第三通孔和所述第四通孔中填充第三金属,以于所述第三通孔中形成第三金属孔连线,于所述第四通孔中形成第四金属孔连线;
步骤S5、制备顶层金属薄膜覆盖所述第三金属孔连线、所述第四金属孔连线和所述第四绝缘层的上表面;刻蚀所述顶层金属薄膜,以形成若干引线和若干平行排列的顶部金属导线;
其中,各所述引线均通过所述第四金属孔连线将所述磁芯连接,所述顶部金属导线依次通过所述第三金属孔连线、所述第二金属孔连线和所述第一金属孔连线将所述底部金属导线首尾依次连接。
较佳的,上述的立体集成电感电容结构的制备方法,其中,步骤S5中,与所述底部金属导线在垂直投影方向上构成一定夹角刻蚀所述顶层金属薄膜以形成所述顶部金属导线。
较佳的,上述的立体集成电感电容结构的制备方法,其中,所述第一金属与所述第三金属的材质相同。
较佳的,上述的立体集成电感电容结构的制备方法,其中,所述第一金属与所述第三金属的材质为钨或锡。
较佳的,上述的立体集成电感电容结构的制备方法,其中,所述第二金属的材质为钴或镍。
较佳的,上述的立体集成电感电容结构的制备方法,其中,所述底层金属薄膜与所述顶层金属薄膜的材质相同。
较佳的,上述的立体集成电感电容结构的制备方法,其中,所述第一绝缘层、所述第二绝缘层、所述第三绝缘层和所述第四绝缘层的材质均相同。
较佳的,上述的立体集成电感电容结构的制备方法,其中,步骤S2~S5中,任一填充金属或者制备绝缘层工艺之后均需要进行化学机械抛光工艺。
上述技术方案具有如下优点或有益效果:
本发明公开了一种立体集成电感电容结构的制备方法,可以实现三维立体结构的电感电容,通过制备顶部金属导线与底部金属导线互联形成以磁芯为中心单方向绕行的立体螺旋状的电感线圈,可以在相对较小的空间中同时获取电容电感,降低了电容电感的制作成本,同时也极大的提高了电感磁通量以增加电感值并降低涡旋电流,并提高品质因数Q值以及电感线圈的性能。
具体附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述,本发明及其特征、外形和优点将会变得更加明显。在全部附图中相同的标记指示相同的部分。并未可以按照比例绘制附图,重点在于示出本发明的主旨。
图1是本发明中立体集成电感电容的结构示意图;
图2是本发明中立体集成电感电容结构的侧面剖面的结构示意图;
图3a~7b是本发明中立体集成电感电容结构的制备工艺流程图。
具体实施方式
下面结合附图和具体的实施例对本发明作进一步的说明,但是不作为本发明的限定。
为可以在提高电感磁通量以增加电感值的同时降低涡旋电流,并提高品质因数Q值以及电感线圈的性能,我们需要制备一种立体集成电感电容结构。
如图1所示,该立体集成电感电容结构包括第一电容和第二电容,第一电容和第二电容均是由截面积逐渐递增的若干金属框架1在同一平面内相互嵌套形成,且金属框架相互电连接形成电容极板(图1中未示出)。
优选的,第一电容与第二电容在同一平面内且互不接触,第一电容极板与第二电容极板间均填充绝缘介质5,该结构设计可以在较小的空间内提高电容的性能。
另外该结构还包括一电感线圈,如图1所示,具体包括若干均匀平行分布的第一金属线2和若干均匀平行分布的第二金属线3,第一金属线2和第二金属线3分别位于金属框架1所在的平面的两侧,且第一金属线2与第二金属线3的首端(也包括第一金属线2与第二金属线3的末端)投影重合且均垂直于电容的最内侧金属框架1内。优选的,第一金属线2所在平面、第二金属线3所在平面与金属框架1所在平面相互平行。其中,电感线圈还包括一第三金属线4,第三金属线4垂直穿过截面积最小的金属框架1内区域,使其可以达到如下效果:
第一金属线2的首端通过第三金属线4连接与第一金属线2首端垂直方向上的投影重合的第二金属线3的首端,且与第一金属线2首端垂直方向上的投影重合的第二金属线3的末端通过另一第三金属线4连接第一金属线2相邻的另一第一金属线2的末端,形成单方向绕行并呈立体螺旋状的电感线圈(以金属框架为磁芯),另外金属框架1可通过金属引线6电连接形成电容极板,如图2所示。
基于上述结构,本发明提供一种立体集成电感电容结构的制备方法:
步骤S1、对一半导体衬底进行加工,具体的在该半导体衬底11之上依次制备第一绝缘层12(沉积绝缘层后需快速的进行热退火工艺,使其形成致密的绝缘层)和底层金属薄膜,并去除部分底层金属薄膜,使其在第一绝缘层12上方形成若干底部金属导线13,其中所有的底部金属导线13平行排列在第一绝缘层12的上表面,如图3a和3b所示。
在本发明的实施例中,上述的底层金属薄膜的材质为铝金属,且底部金属导线13作为上述电感线圈的第二金属线3.
步骤S2、采用等离子体化学气相沉积法在上述若干平行排列的底部金属导线13的上表面以及在第一绝缘层12暴露的上表面继续沉积第二绝缘层14,然后采用电感耦合等离子体(Inductively Coupled Plasma,简称ICP)或者反应离子刻蚀(Reactive IonEtching,简称RIE)等工艺刻蚀该第二绝缘层14,以于各底部金属导线的长度延伸方向的两端端部区域之上均形成一第一通孔。
在本发明的实施例中,在该第一通孔填充第一金属,形成位于底部金属导线13上方的两列第一金属孔连线15,如图4a和4b所示。
在本发明的实施例中,第一金属的材质优选为钨或锡材料。
同时为了优化立体集成电感的制备工艺,需要在淀积第二绝缘层14和于第一通孔中填充第一金属后均需要进行化学机械抛光(Chemical mechanical polishing,简称CMP)工艺。
优选的,第二绝缘层14与第一绝缘层12的材质相同,可选为二氧化硅。
步骤S3、继续采用等离子体化学气相沉积法在第二绝缘层14和第一金属孔连线15的上表面淀积第三绝缘层16,优选的,该第三绝缘层16的材质与第二绝缘层14的材质相同。然后采用ICP或者RIE工艺刻蚀部分第三绝缘层16,形成位于将每一个第一金属孔连线15上表面予以暴露的一个第二通孔以及若干环状凹槽,其中该若干环状凹槽均环绕设置在第二通孔周围。
在本发明的实施例中,优选的该环状凹槽的数量至少为2个,例如3个。
为了提高立体集成电感电容的性能,本发明实施例中需要提供磁芯,来增强磁能的存储效果,因此在完成环状凹槽与第二通孔工艺之后于环状凹槽和第二通孔中填充第二金属(如钴,镍等)形成每个第一金属孔连线上方的一个第二金属孔连线18以及若干磁芯17,如图5a和5b所示。
其中,上述若干磁芯17构成上述金属框架1(或者第一电容和第二电容)。
在本发明的实施例中,为了优化立体集成电感的制备工艺,需要在淀积第三绝缘层16和于第二通孔、环状凹槽中填充第二金属后均需要进行CMP工艺。
步骤S4、继续采用等离子体化学气相沉积法在第三绝缘层16、第二金属孔连线18以及磁芯17的上表面淀积第四绝缘层19,然后采用ICP或者RIE刻蚀工艺刻蚀第四绝缘层19,形成每一个第二金属孔连线18上方的一个第三通孔并予以暴露第二金属孔连线18,以及位于每个磁芯17上方的一个第四通孔。
继续在第三通孔和第四通孔中填充第三金属,以于第三通孔中形成第三金属孔连线20,并以于第四通孔中形成第四金属孔连线201。
在本发明的实施例中,优选的,第三金属与第一金属的材质相同,为钨或锡材料,如图6a和6b所示。
同样,淀积第四绝缘层19以及填充金属材料之后需要进行CMP工艺,优化立体集成电感电容结构的制备工艺。
优选的,第一绝缘层12、第二绝缘层14、第三绝缘层16和第四绝缘层19的材质均相同,更优选的其材质均为二氧化硅。
步骤S5、在第三金属孔连线20、第四金属孔连线201以及第四绝缘层19的上表面继续淀积一顶层金属薄膜,刻蚀该顶层金属薄膜形成若干平行排列的顶部金属导线21以及每个第四金属孔连线201上方的每个引线211,如图7a和7b所示。
在本发明的实施例中,与底部金属导线13在垂直投影方向上构成一定夹角刻蚀该顶层金属薄膜以形成上述顶部金属导线21,也就是说,底部金属导线13与顶部金属导线21在垂直投影方向上构成一定夹角,便于后续形成螺旋状电感线圈,该顶部金属导线21作为上述电感线圈的第一金属线2。
其中,各引线211均通过第四金属孔连线201将所述磁芯17连接,形成上述电容极板;各第一金属孔连线15、第二金属孔连线18以及第三金属孔连线20构成上述第三金属线4,且各顶部金属导线21通过第三金属孔连线20、第二金属孔连线18和第一金属孔连线15将底部金属导线13首尾依次连接,最终形成上述螺旋状的电感线圈。
综上所述,本发明公开了一种立体集成电感电容结构的制备方法,可以实现三维立体结构的电感电容,通过制备顶部金属导线与底部金属导线互联形成以磁芯为中心单方向绕行的立体螺旋状的电感线圈,可以在相对较小的空间中同时获取电容电感,降低了电容电感的制作成本,同时也极大的提高了电感磁通量以增加电感值并降低涡旋电流,并提高品质因数Q值以及电感线圈的性能。
本领域技术人员应该理解,本领域技术人员在结合现有技术以及上述实施例可以实现所述变化例,在此不做赘述。这样的变化例并不影响本发明的实质内容,在此不予赘述。
以上对本发明的较佳实施例进行了描述。需要理解的是,本发明并不局限于上述特定实施方式,其中未尽详细描述的设备和结构应该理解为用本领域中的普通方式予以实施;任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案做出许多可能的变动和修饰,或修改为等同变化的等效实施例,这并不影响本发明的实质内容。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (8)
1.一种立体集成电感电容结构的制备方法,其特征在于,所述方法包括:
步骤S1、提供一半导体衬底,并于所述半导体衬底之上依次制备第一绝缘层和底层金属薄膜,并去除部分所述底层金属薄膜,以于所述第一绝缘层之上形成若干平行排列的底部金属导线;
步骤S2、制备第二绝缘层覆盖所述底部金属导线及所述第一绝缘层暴露的表面,并刻蚀所述第二绝缘层,以于各所述底部金属导线的长度延伸方向的两端部区域之上均形成一第一通孔;
于所述第一通孔中填充第一金属,以于所述底部金属导线之上形成两列第一金属孔连线;
步骤S3、制备第三绝缘层覆盖所述第一金属孔连线和所述第二绝缘层的上表面,并刻蚀第三绝缘层,以于各所述第一金属孔连线之上形成一第二通孔及若干环状凹槽,且各第二通孔外均设置有环绕所述第二通孔的至少两个所述环状凹槽;
于所述第二通孔和所述环状凹槽中填充第二金属,以于各所述第一金属孔连线之上均形成第二金属孔连线和若干环状的磁芯;
步骤S4、制备第四绝缘层覆盖所述第二金属孔连线、所述磁芯和所述第三绝缘层的上表面,并刻蚀第四绝缘层,以于各所述第二金属孔连线之上均形成一第三通孔和位于各磁芯之上的一第四通孔;
于所述第三通孔和所述第四通孔中填充第三金属,以于所述第三通孔中形成第三金属孔连线,于所述第四通孔中形成第四金属孔连线;
步骤S5、制备顶层金属薄膜覆盖所述第三金属孔连线、所述第四金属孔连线和所述第四绝缘层的上表面;刻蚀所述顶层金属薄膜,以形成若干引线和若干平行排列的顶部金属导线;
其中,各所述引线均通过所述第四金属孔连线将所述磁芯连接,所述顶部金属导线依次通过所述第三金属孔连线、所述第二金属孔连线和所述第一金属孔连线将所述底部金属导线首尾依次连接。
2.如权利要求1所述的立体集成电感电容结构的制备方法,其特征在于,步骤S5中,与所述底部金属导线在垂直投影方向上构成一定夹角刻蚀所述顶层金属薄膜以形成所述顶部金属导线。
3.如权利要求1所述的立体集成电感电容结构的制备方法,其特征在于,所述第一金属与所述第三金属的材质相同。
4.如权利要求3所述的立体集成电感电容结构的制备方法,其特征在于,所述第一金属与所述第三金属的材质为钨或锡。
5.如权利要求1所述的立体集成电感电容结构的制备方法,其特征在于,所述第二金属的材质为钴或镍。
6.如权利要求1所述的立体集成电感电容结构的制备方法,其特征在于,所述底层金属薄膜与所述顶层金属薄膜的材质相同。
7.如权利要求1所述的立体集成电感电容结构的制备方法,其特征在于,所述第一绝缘层、所述第二绝缘层、所述第三绝缘层和所述第四绝缘层的材质均相同。
8.如权利要求1所述的立体集成电感电容结构的制备方法,其特征在于,步骤S2~S5中,任一填充金属或者制备绝缘层工艺之后均需要进行化学机械抛光工艺。
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