JP2520527Y2 - リードフレーム - Google Patents
リードフレームInfo
- Publication number
- JP2520527Y2 JP2520527Y2 JP1990102383U JP10238390U JP2520527Y2 JP 2520527 Y2 JP2520527 Y2 JP 2520527Y2 JP 1990102383 U JP1990102383 U JP 1990102383U JP 10238390 U JP10238390 U JP 10238390U JP 2520527 Y2 JP2520527 Y2 JP 2520527Y2
- Authority
- JP
- Japan
- Prior art keywords
- island
- bonding
- lead frame
- suspension
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000725 suspension Substances 0.000 claims description 18
- 238000003466 welding Methods 0.000 description 6
- 230000002950 deficient Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990102383U JP2520527Y2 (ja) | 1990-09-29 | 1990-09-29 | リードフレーム |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1990102383U JP2520527Y2 (ja) | 1990-09-29 | 1990-09-29 | リードフレーム |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0459956U JPH0459956U (en, 2012) | 1992-05-22 |
JP2520527Y2 true JP2520527Y2 (ja) | 1996-12-18 |
Family
ID=31846594
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1990102383U Expired - Lifetime JP2520527Y2 (ja) | 1990-09-29 | 1990-09-29 | リードフレーム |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2520527Y2 (en, 2012) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2735509B2 (ja) * | 1994-08-29 | 1998-04-02 | アナログ デバイセス インコーポレーテッド | 改善された熱放散を備えたicパッケージ |
JP4590961B2 (ja) * | 2004-07-20 | 2010-12-01 | 株式会社デンソー | 電子装置 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5910249A (ja) * | 1982-07-09 | 1984-01-19 | Nec Corp | 半導体装置用リ−ドフレ−ム |
JPS6070755A (ja) * | 1983-09-28 | 1985-04-22 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
JPS60105747A (ja) * | 1983-11-14 | 1985-06-11 | 株式会社イナックス | タイルパネル構成体を利用した吊天井構造 |
JPS60123046A (ja) * | 1983-12-07 | 1985-07-01 | Toshiba Corp | 半導体装置 |
JPS60119756U (ja) * | 1984-01-20 | 1985-08-13 | 三洋電機株式会社 | リ−ドフレ−ム |
JPS639149U (en, 2012) * | 1986-07-03 | 1988-01-21 | ||
JP2539611B2 (ja) * | 1986-10-27 | 1996-10-02 | ロ−ム株式会社 | 半導体装置の製造方法 |
JPH01143246A (ja) * | 1987-11-30 | 1989-06-05 | Nec Corp | 半導体装置 |
JPH01244654A (ja) * | 1988-03-25 | 1989-09-29 | Nec Kyushu Ltd | リードフレーム |
JPH02174254A (ja) * | 1988-12-27 | 1990-07-05 | Nec Corp | Icパッケージ |
-
1990
- 1990-09-29 JP JP1990102383U patent/JP2520527Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0459956U (en, 2012) | 1992-05-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
EXPY | Cancellation because of completion of term |