JP2025504525A5 - - Google Patents
Info
- Publication number
- JP2025504525A5 JP2025504525A5 JP2024543908A JP2024543908A JP2025504525A5 JP 2025504525 A5 JP2025504525 A5 JP 2025504525A5 JP 2024543908 A JP2024543908 A JP 2024543908A JP 2024543908 A JP2024543908 A JP 2024543908A JP 2025504525 A5 JP2025504525 A5 JP 2025504525A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- donor substrate
- process according
- electrical insulating
- insulating layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2200849A FR3132380B1 (fr) | 2022-01-31 | 2022-01-31 | Procédé de fabrication d’une structure de type double semi-conducteur sur isolant |
| FR2200849 | 2022-01-31 | ||
| PCT/FR2023/050116 WO2023144496A1 (fr) | 2022-01-31 | 2023-01-30 | Procédé de fabrication d'une structure de type double semi-conducteur sur isolant |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025504525A JP2025504525A (ja) | 2025-02-12 |
| JP2025504525A5 true JP2025504525A5 (https=) | 2025-12-08 |
Family
ID=81449054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024543908A Pending JP2025504525A (ja) | 2022-01-31 | 2023-01-30 | 二重半導体オンインシュレータ構造を作製するためのプロセス |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20250140601A1 (https=) |
| EP (1) | EP4473560A1 (https=) |
| JP (1) | JP2025504525A (https=) |
| KR (1) | KR20240142524A (https=) |
| CN (1) | CN118633150A (https=) |
| FR (1) | FR3132380B1 (https=) |
| TW (1) | TW202347607A (https=) |
| WO (1) | WO2023144496A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117594522A (zh) * | 2023-12-25 | 2024-02-23 | 中国科学院微电子研究所 | 一种新型绝缘体上硅晶圆及其制备方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3975634B2 (ja) * | 2000-01-25 | 2007-09-12 | 信越半導体株式会社 | 半導体ウェハの製作法 |
| US7160753B2 (en) * | 2004-03-16 | 2007-01-09 | Voxtel, Inc. | Silicon-on-insulator active pixel sensors |
| JP5673572B2 (ja) * | 2012-01-24 | 2015-02-18 | 信越半導体株式会社 | 貼り合わせｓｏｉウェーハの製造方法 |
| FR2987935B1 (fr) * | 2012-03-12 | 2016-07-22 | Soitec Silicon On Insulator | Procede d'amincissement de la couche active de silicium d'un substrat du type "silicium sur isolant" (soi). |
-
2022
- 2022-01-31 FR FR2200849A patent/FR3132380B1/fr active Active
-
2023
- 2023-01-30 WO PCT/FR2023/050116 patent/WO2023144496A1/fr not_active Ceased
- 2023-01-30 EP EP23706412.6A patent/EP4473560A1/fr active Pending
- 2023-01-30 KR KR1020247029136A patent/KR20240142524A/ko active Pending
- 2023-01-30 JP JP2024543908A patent/JP2025504525A/ja active Pending
- 2023-01-30 US US18/834,746 patent/US20250140601A1/en active Pending
- 2023-01-30 TW TW112103175A patent/TW202347607A/zh unknown
- 2023-01-30 CN CN202380019046.5A patent/CN118633150A/zh active Pending
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