TW202347607A - 用於製作雙重絕緣體上半導體結構之方法 - Google Patents

用於製作雙重絕緣體上半導體結構之方法 Download PDF

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Publication number
TW202347607A
TW202347607A TW112103175A TW112103175A TW202347607A TW 202347607 A TW202347607 A TW 202347607A TW 112103175 A TW112103175 A TW 112103175A TW 112103175 A TW112103175 A TW 112103175A TW 202347607 A TW202347607 A TW 202347607A
Authority
TW
Taiwan
Prior art keywords
semiconductor layer
substrate
donor substrate
transferred
insulating layer
Prior art date
Application number
TW112103175A
Other languages
English (en)
Chinese (zh)
Inventor
凱琳 杜瑞特
魯多維克 伊卡諾
夏琳 波塔
Original Assignee
法商索泰克公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 法商索泰克公司 filed Critical 法商索泰克公司
Publication of TW202347607A publication Critical patent/TW202347607A/zh

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • H10P90/1916Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/64Wet etching of semiconductor materials
    • H10P50/642Chemical etching
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40Chemomechanical polishing [CMP]
    • H10P52/402Chemomechanical polishing [CMP] of semiconductor materials

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  • Element Separation (AREA)
TW112103175A 2022-01-31 2023-01-30 用於製作雙重絕緣體上半導體結構之方法 TW202347607A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FRFR2200849 2022-01-31
FR2200849A FR3132380B1 (fr) 2022-01-31 2022-01-31 Procédé de fabrication d’une structure de type double semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
TW202347607A true TW202347607A (zh) 2023-12-01

Family

ID=81449054

Family Applications (1)

Application Number Title Priority Date Filing Date
TW112103175A TW202347607A (zh) 2022-01-31 2023-01-30 用於製作雙重絕緣體上半導體結構之方法

Country Status (8)

Country Link
US (1) US20250140601A1 (https=)
EP (1) EP4473560A1 (https=)
JP (1) JP2025504525A (https=)
KR (1) KR20240142524A (https=)
CN (1) CN118633150A (https=)
FR (1) FR3132380B1 (https=)
TW (1) TW202347607A (https=)
WO (1) WO2023144496A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117594522A (zh) * 2023-12-25 2024-02-23 中国科学院微电子研究所 一种新型绝缘体上硅晶圆及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
JP5673572B2 (ja) * 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
FR2987935B1 (fr) * 2012-03-12 2016-07-22 Soitec Silicon On Insulator Procede d'amincissement de la couche active de silicium d'un substrat du type "silicium sur isolant" (soi).

Also Published As

Publication number Publication date
FR3132380B1 (fr) 2024-11-29
US20250140601A1 (en) 2025-05-01
WO2023144496A1 (fr) 2023-08-03
JP2025504525A (ja) 2025-02-12
EP4473560A1 (fr) 2024-12-11
CN118633150A (zh) 2024-09-10
KR20240142524A (ko) 2024-09-30
FR3132380A1 (fr) 2023-08-04

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