JP2025504525A - 二重半導体オンインシュレータ構造を作製するためのプロセス - Google Patents

二重半導体オンインシュレータ構造を作製するためのプロセス Download PDF

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Publication number
JP2025504525A
JP2025504525A JP2024543908A JP2024543908A JP2025504525A JP 2025504525 A JP2025504525 A JP 2025504525A JP 2024543908 A JP2024543908 A JP 2024543908A JP 2024543908 A JP2024543908 A JP 2024543908A JP 2025504525 A JP2025504525 A JP 2025504525A
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JP
Japan
Prior art keywords
semiconductor layer
donor substrate
substrate
transferred
electrically insulating
Prior art date
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Pending
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JP2024543908A
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English (en)
Japanese (ja)
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JP2025504525A5 (https=
Inventor
カリーヌ デュレ，
ルドヴィック エカルノ，
シャルレーヌ ポルタ，
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Soitec SA
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Soitec SA
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Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of JP2025504525A publication Critical patent/JP2025504525A/ja
Publication of JP2025504525A5 publication Critical patent/JP2025504525A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials

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JP2024543908A 2022-01-31 2023-01-30 二重半導体オンインシュレータ構造を作製するためのプロセス Pending JP2025504525A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2200849A FR3132380B1 (fr) 2022-01-31 2022-01-31 Procédé de fabrication d’une structure de type double semi-conducteur sur isolant
FR2200849 2022-01-31
PCT/FR2023/050116 WO2023144496A1 (fr) 2022-01-31 2023-01-30 Procédé de fabrication d'une structure de type double semi-conducteur sur isolant

Publications (2)

Publication Number Publication Date
JP2025504525A true JP2025504525A (ja) 2025-02-12
JP2025504525A5 JP2025504525A5 (https=) 2025-12-08

Family

ID=81449054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024543908A Pending JP2025504525A (ja) 2022-01-31 2023-01-30 二重半導体オンインシュレータ構造を作製するためのプロセス

Country Status (8)

Country Link
US (1) US20250140601A1 (https=)
EP (1) EP4473560A1 (https=)
JP (1) JP2025504525A (https=)
KR (1) KR20240142524A (https=)
CN (1) CN118633150A (https=)
FR (1) FR3132380B1 (https=)
TW (1) TW202347607A (https=)
WO (1) WO2023144496A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117594522A (zh) * 2023-12-25 2024-02-23 中国科学院微电子研究所 一种新型绝缘体上硅晶圆及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
JP5673572B2 (ja) * 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
FR2987935B1 (fr) * 2012-03-12 2016-07-22 Soitec Silicon On Insulator Procede d'amincissement de la couche active de silicium d'un substrat du type "silicium sur isolant" (soi).

Also Published As

Publication number Publication date
FR3132380B1 (fr) 2024-11-29
US20250140601A1 (en) 2025-05-01
WO2023144496A1 (fr) 2023-08-03
EP4473560A1 (fr) 2024-12-11
CN118633150A (zh) 2024-09-10
TW202347607A (zh) 2023-12-01
KR20240142524A (ko) 2024-09-30
FR3132380A1 (fr) 2023-08-04

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