Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
  • H10P90/19—Preparing inhomogeneous wafers
  • H10P90/1904—Preparing vertically inhomogeneous wafers
  • H10P90/1906—Preparing SOI wafers
  • H10P90/1914—Preparing SOI wafers using bonding
  • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/90—Thermal treatments, e.g. annealing or sintering
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
  • H10W10/10—Isolation regions comprising dielectric materials
  • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
  • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
  • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P50/00—Etching of wafers, substrates or parts of devices
  • H10P50/60—Wet etching
  • H10P50/64—Wet etching of semiconductor materials
  • H10P50/642—Chemical etching
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
  • H10P52/40—Chemomechanical polishing [CMP]
  • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials

Definitions

• the invention relates to a method for manufacturing a structure of the double semiconductor on insulator type.
• Structures of the semiconductor-on-insulator type are multilayer structures comprising a support substrate which is generally made of a semiconductor material such as silicon, an electrically insulating layer arranged on the support substrate, which is generally an oxide layer such a layer of silicon oxide, and a semiconductor layer arranged on the insulating layer, which is generally a layer of silicon.
• Such structures are called “Semiconductor on Insulator” structures in English, in particular “Silicon on Insulator” (SOI) when the semiconductor material is silicon.
• SOI Silicon on Insulator
• the oxide layer is between the substrate and the semiconductor layer.
• the oxide layer is then called “buried", and is called “BOX” for "Buried Oxide” in English.
• SOI will be used to generally designate structures of the semiconductor-on-insulator type.
• double SOI structures In addition to SOI structures comprising a BOX layer and a semiconductor layer arranged on the BOX layer, “double SOI” structures have been produced.
• the "double SOI” structures comprise a support substrate ("handle substrate", a first oxide layer or lower buried oxide layer arranged on the support substrate, a first semi-conductor layer or lower semi-conductor layer arranged on the first oxide layer, a second oxide layer or upper buried oxide layer arranged on the first semiconductor layer and a second semiconductor layer or upper semiconductor layer arranged on the second oxide.
• the first oxide layer and the first semiconductor layer constitute the first SOI, arranged in a lower part of the structure
• the second oxide layer and the second semiconductor layer constitute the second SOI, arranged in an upper part of the structure.
• a known process for manufacturing an SOI structure is the so-called Smart CutTM process.
• the Smart CutTM process includes the implantation of atomic species, such as hydrogen (H) and/or helium (He), in order to create a zone of weakness within a donor substrate, the bonding of the donor substrate on the receiver substrate by means of an electrically insulating layer then the detachment of the donor substrate at the weakened zone so as to transfer a thin layer of the donor substrate onto the receiver substrate.
• the donor substrate and the receiver substrate are preferably in the form of plates 300 mm in diameter of a semiconductor material.
• the electrically insulating layer can be formed on the donor substrate or on the receiver substrate.
• a proposed solution for obtaining a double SOI is to implement two successive Smart CutTM processes.
• the SOI obtained following the first Smart CutTM process is used as a second receiver substrate on which a second donor substrate is bonded via a second electrically insulating layer.
• the effectiveness of the bonding during the second Smart CutTM process is conditioned by the quality of the surface of the first SOI serving as the receiving substrate. In particular, it depends on the roughness and the defectiveness of said surface after the detachment of the first donor substrate along the embrittlement zone during the first Smart CutTM process. Indeed, during bonding during the second Smart CutTM process, defects and other surface irregularities induce the formation of holes between the receiver substrate and the second donor substrate within the final double SOI. Said holes most often harm the electrical performance of the structure and the mechanical strength of the assembly.
• Surface treatments can be implemented in order to reduce the roughness and the defectiveness of the surface of the first SOI following the detachment of the first donor substrate.
• An object of the invention is to propose a process for manufacturing a structure of the double semiconductor on insulator type which guarantees good bonding of the donor substrate of the second semiconductor layer on a receiver substrate resulting from a first process. Smart CutTM.
• the invention proposes a method for manufacturing a structure of the double semiconductor on insulator type comprising the following steps:
• a first electrically insulating layer being at the interface between the support substrate and the first donor substrate, and detachment of the first donor substrate at the weakened zone, so as to obtain a semiconductor-on-insulator type structure comprising, from the rear face to the front face, the support substrate, the first electrically insulating layer and the first transferred semiconductor layer,
• a second electrically insulating layer being at the interface between the transferred first semiconductor layer and the second donor substrate, in which the treatment of the surface of the first transferred semiconductor layer comprises the following successive steps:
• the free surface of the first semiconductor layer results from the detachment of the first donor substrate along the zone of weakness.
• the process for treating said surface is optimized to reduce its roughness and defectivity.
• Said method also makes it possible to reduce the width of the crown on the outer edge of the second receiver substrate.
• the joint decrease in defectivity, roughness, crown width and crown irregularity (a phenomenon known as "jagged edge” in English) on the outer edge of the plates limits the number of holes formed during bonding of the donor substrate of the second semiconductor layer.
• step E3 of smoothing heat treatment is a long-term thermal annealing carried out at a temperature between 1050 ° C and 1250 ° C for a few minutes to a few hours under an atmosphere of pure Argon or Hydrogen or in a mixture ;
• the heat treatment step E3 is rapid thermal annealing
• step E3 of rapid thermal annealing is carried out at a temperature between 1100°C and 1250°C for a few seconds to around a hundred seconds, under an atmosphere comprising pure Argon or Hydrogen or a mixture thereof ;
• step E1 of rapid thermal annealing is carried out at a temperature between 1100°C and 1250°C for a few seconds to around one hundred seconds, under an atmosphere comprising pure Argon or Hydrogen or a mixture thereof ;
• step E2 the thermal oxidation operation of step E2 is carried out at a temperature of between 800°C and 1100°C in an atmosphere comprising oxygen or water vapor for a few minutes to a few hours;
• step E2 the deoxidation operation of step E2 is carried out by exposing the surface to be treated to a solution of hydrofluoric acid;
• each donor substrate is in the form of a plate 300 mm in diameter
• the embrittlement zone in the first donor substrate is formed by implantation of hydrogen atoms
• a second electrically insulating layer being at the interface between the front face of the semiconductor-on-insulator type structure and the first substrate giver
• the detachment of the second donor substrate at the weakened zone so as to obtain a structure of the double semiconductor on insulator type comprising, from the rear face towards the front face, the support substrate, the first electrically insulating layer, the first transferred semiconductor layer, the second electrically insulating layer and the second transferred semiconductor layer;
• the embrittlement zone in the second donor substrate is formed by implantation of hydrogen atoms;
• the second electrically insulating layer is formed by oxidation of the front face of the transferred first semiconductor layer, so that, during the transfer of the second semiconductor layer, said first electrically insulating layer is inserted between the first layer semiconductor and the second semiconductor layer, said additional oxidation step being implemented after the treatment of the free surface of the first semiconductor layer;
• the second electrically insulating layer is formed by oxidation of a part of the second donor substrate, so that, during the transfer of the second semiconductor layer, said first electrically insulating layer is also transferred and is inserted between the first layer semiconductor and said second semiconductor layer;
• the first electrically insulating layer is formed by oxidation of the front face of the support substrate prior to bonding the first donor substrate to the support substrate so that said first electrically insulating layer is inserted between the support substrate and the first semiconductor layer transferred;
• the first electrically insulating layer is formed by oxidation of a part of the first donor substrate prior to the bonding of said first donor substrate on the support substrate by its oxidized face so that said first electrically insulating layer is inserted between the support substrate and the first semiconductor layer transferred.
• FIG. 1 shows a sectional view of the intermediate structure of semiconductor-on-insulator type obtained following the first layer transfer
• FIG. 2 shows a sectional view of a first layer transfer by a first donor substrate on the front face of the support substrate, the first electrically insulating layer being formed on the surface of the first donor substrate,
• FIG. 3 shows a sectional view of a first layer transfer by a first donor substrate on the front face of the support substrate, the first electrically insulating layer being formed on the surface of the support substrate,
• FIG. 4 is a diagram representing the sequence of processing steps according to the method of the invention.
• FIG. 6 shows a sectional view of a second monocrystalline semiconductor layer transfer by a second donor substrate, the second electrically insulating layer being formed on the second donor substrate
• FIG. 7 shows a sectional view of a second monocrystalline semiconductor layer transfer by a second donor substrate, the second electrically insulating layer being formed on the structure of Figure 2.
• a structure of the semi-conductor on insulator double substrate type comprises, from the rear face towards the front face, a support substrate, a first buried oxide layer corresponding to a first electrically insulating layer, a first single-crystal semiconductor layer, a second buried oxide layer corresponding to a second electrically insulating layer and a second monocrystalline semiconductor layer.
• the first electrically insulating layer and the first single-crystal semiconductor layer together form a first semiconductor-on-insulator type structure called a lower SOI structure.
• the second electrically insulating layer and the second monocrystalline semiconductor layer together form a second semiconductor-on-insulator type structure called an upper SOI structure.
• the invention relates to a method for preparing a structure of the double semiconductor on insulator type comprising in particular:
• the invention relates more particularly to the intermediate surface treatment process implemented following the SmartCutTM process for the transfer of the first single-crystal semiconductor layer, the SmartCutTM process and other layer transfer processes being known elsewhere. .
• the surface treatment method of the invention has been optimized so as to minimize the roughness and the defectiveness of a surface formed following the implementation of said first SmartCutTM method so as to improve the quality of the bonding during the second transfer. of layer.
• roughness means the maximum peak-to-valley amplitude measured by atomic force microscopy (AFM) on surface profiles between 1x1 pm 2 and 30x30 pm 2 .
• the defectivity it is defined as being the number of particles deposited on the free surface of the plate, and/or the number of structural defects such as holes or scratches present on the surface of the plate. These defects are of various sizes, for example between 60 nm and several microns. The defects can come from impurities created by the local detachment of the irregular edge of the crown (“jagged edge”) or from contamination. Defectiveness is measured using equipment using a light scattering technique such as SP2 equipment from KLA Tencor.
• the method also aims to widen the effective bonding area of the second transferred layer so as to reduce the width of the peripheral crown of the second SOI substrate.
• the peripheral region of an SOI substrate where the transfer of the monocrystalline semiconductor layer has not taken place is called the crown.
• This crown is due to the fact that the substrates conventionally have a peripheral chamfer a few millimeters wide, at which bonding of the donor substrate to the receiver substrate cannot be ensured.
• the monocrystalline semiconductor layer of the donor substrate is therefore only transferred to the receiver substrate in the central zone where the bonding took place. In some cases, however, a transfer of isolated areas of the donor substrate into the crown may occur.
• the crown then does not have a perfectly circular shape, but an irregular jagged edge (“jagged edge” according to the English name).
• the irregular crown problem therefore occurs twice: during the manufacture of the first SOI substrate then during the manufacture of the second SOI substrate, and therefore has a significant impact on the useful width of the upper semiconductor layer.
• the width of the crown at the end of the first layer transfer is typically between 0.7 mm and 1.5 mm
• the width of the "double crown" at the end of the second layer transfer is comprised between 3mm and 4mm.
• the surface treatment method in accordance with the invention is characterized in that it comprises four successive steps, each step being a surface treatment which is known elsewhere, making it possible to act on one or other of the parameters defined below. below.
• the first semiconductor-on-insulator type structure or lower SOI structure is prepared by a first transfer of a single-crystal semiconductor layer. Said structure is shown in Figure 1 . Said first transfer is carried out by a Smart CutTM process which includes the following steps:
• a first electrically insulating layer 2a being at the interface between the support substrate 1 and the first donor substrate
• the support substrate 1 is in the form of a circular plate of a semiconductor material, preferably a plate 300 mm in diameter.
• the support substrate is for example a silicon wafer.
• the support substrate is preferably an ultra-flat silicon wafer, which has a narrower and steeper bevel than on conventional wafers.
• the width of the edge chamfer of the plates can be evaluated using the characteristic ZDD148 which corresponds to the second derivative of the edge profile of the plate at 2 mm from the edge of the plate, in other words the inverse of the radius of curvature of this plate edge.
• ZDD148 of silicon wafers 300 mm in diameter is between ⁇ 20 and ⁇ 200 nm/mm 2 .
• ZDD148 is measured using WAFERSIGHT equipment from KLA TENCOR.
• a so-called ultra-flat silicon wafer has a ZDD148 characteristic of between 0 to ⁇ 20 nm/mm 2 .
• the use of an ultra-flat silicon plate makes it possible to reduce the width of the peripheral crown.
• the first donor substrate is a monocrystalline semiconductor substrate, for example a monocrystalline silicon substrate.
• the first donor substrate is in the form of a plate which is generally of the same diameter as the support substrate.
• the embrittlement zone can be created by co-implantation of helium atoms and hydrogen atoms in the first donor substrate of the first semiconductor layer. Helium and hydrogen are implanted with energies comprised between 10 keV and 100 keV and the implanted doses are comprised between 10 15 atoms per cm 2 and 10 17 atoms per cm 2 . Alternatively, the embrittlement zone is preferentially created by implantation of hydrogen atoms.
• the co-implantation of hydrogen and helium atoms has the advantage of allowing a sharper fracture of the donor substrate along the embrittlement zone, which results in a lower roughness of the transferred semiconductor layer. , of the order of 50.10 -10 m RMS or 60. 10 -10 m RMS (i.e.
• the implantation of hydrogen atoms alone has the advantage of overcoming the “jagged edge” phenomenon but on the other hand provides a greater roughness of the transferred semiconductor layer.
• the roughness measured by AFM 30 ⁇ 30 ⁇ m 2 is in this case of the order of 80.10 ⁇ 10 m RMS (ie 80 ⁇ RMS).
• the treatment described below makes it possible to obtain a final surface of the first transferred semiconductor layer that is sufficiently smooth to allow the formation of the second SOI substrate. Consequently, in view of the advantage presented in terms of limiting the “jagged edge”, the implantation of hydrogen atoms alone will be preferred to the co-implantation of hydrogen and helium atoms.
• the detachment along the zone of weakness can be triggered by a mechanical action, a supply of thermal energy, possibly in combination, or any other suitable means.
• the first electrically insulating layer 2a is formed on the first donor substrate prior to the formation of the embrittlement zone within the first donor substrate by implantation of atoms through the first layer electrically insulation 2a.
• the bonding of the first donor substrate to the support substrate 1 is carried out by the electrically insulating face of the said first donor substrate so that the said first electrically insulating layer 2a is transferred at the same time as the first semiconductor layer 2b and is inserted between the support substrate 1 and the first semiconductor layer 2b transferred.
• the first electrically insulating layer 2a is formed for example by oxidation of the front face of the first donor substrate, so that if the first donor substrate is a silicon substrate, the first electrically insulating layer 2a is a layer of silicon oxide.
• the first electrically insulating layer 2a is formed on the front face of the support substrate 1 prior to the bonding of the first donor substrate on said support substrate so that said first electrically insulating layer 2a inserted between the support substrate 1 and the first transferred semiconductor layer 2b.
• the first electrically insulating layer 2a is formed for example by oxidation of the front face of the support substrate 1, so that if the support substrate 1 is a silicon substrate, the first electrically insulating layer 2a is a layer of silicon oxide.
• the front face of the lower SOI structure formed during the detachment of the first donor substrate along the embrittlement zone has a roughness and a defect which are linked to the quality of implantation of the atomic species within the first donor substrate during the implementation of the first Smart CutTM process.
• said roughness can be relatively high, of the order of 50.10 -10 m RMS to 80.10 -10 m RMS (ie from 50 ⁇ RMS to 80 ⁇ RMS) depending on the species implanted.
• the particulate defectivity and the surface roughness can lead, when the second donor substrate is bonded, to the formation of holes or defects.
• a roughness greater than 5.10 ⁇ 10 m RMS (ie 5 ⁇ RMS) generates a density of holes of the order of several holes per cm 2 .
• the holes can cause a malfunction of the devices which will be fabricated from the SOI substrate having said holes. Furthermore, the holes are unevenly distributed on the substrate. This inhomogeneity of the defects induces a strong variability of behavior between the various devices resulting from the same substrate.
• the devices produced on portions of the substrate comprising a high density of holes will not be operational or they will have a high variability in behavior, which is not acceptable for a manufacturer of microelectronic devices, in particular of photonic devices.
• the plate of the support substrate 1 and the plate of the first donor substrate do not have an edge perpendicular to the surface but have a chamfer or "Edge Roll Off".
• the bonding of the first donor substrate to the support substrate is therefore not done over the entire surface of the substrates up to their edge but only up to the chamfer, so that the transferred part of the donor substrate does not extend over the entire surface of the support substrate.
• the peripheral crown is delimited on the outside by the edge of the receiver substrate and on the inside by the edge of the transferred layer. For a 300 mm plate, the peripheral crown CP typically has a width of between 0.7 mm and 1.5 mm relative to the edge of the plate.
• the crown In reality, as mentioned before, the crown often has an irregular shape (the "jagged edge" in English) due to a transitional zone where the bonding did not take place correctly.
• the transient zone represents a potential source of defectivity: parts of said zone can in fact detach and be deposited on the surface of the SOI.
• a surface condition can also lead to the formation of a large number of holes or defects and to a width of the double crown much greater than that of the crown resulting from the first layer transfer, of the order of 3 to 4 mm.
• Such widths are not acceptable, in particular for a photonics application which requires the ability to manufacture chips up to 3 mm from the edge of the silicon wafers.
• the front face of the first semiconductor layer is formed during the detachment of the first donor substrate along the zone of weakness at the end of the Smart CutTM process.
• the invention relates to a method for treating said surface.
• the treatment method in accordance with the invention aims not only to reduce the roughness and defectiveness of said surface, but also to reduce the width of the peripheral ring, thus improving the bonding quality of the second donor substrate.
• the long-term thermal annealing step (E3) can be replaced by a rapid thermal annealing step (E3').
• Rapid thermal annealing means annealing for a period of a few seconds or a few tens of seconds, under a controlled atmosphere. Such annealing is commonly referred to as RTA annealing for “Rapid Thermal Annealing” in English. Rapid thermal annealing (E1) is carried out at a temperature between 1100°C and 1250°C for 1 s to 90 s. Rapid thermal annealing (E1) is carried out under an atmosphere comprising a mixture of argon and hydrogen or an atmosphere of pure argon.
• Rapid thermal annealing reinforces the bonding interface between the support substrate and the transferred semiconductor layer. It also makes it possible to smooth the surface of the transferred semiconductor layer, by causing a reorganization of the atoms present on the surface, and also makes it possible to restore the crystal lattice which may have been disturbed by the implantation. However, it is not sufficient to reach the level of roughness required to allow the bonding of the second donor substrate and then the transfer of a semiconductor layer from the second donor substrate to the first SOI.
• the next oxidation/deoxidation step (E2) must be understood as a sequence comprising the succession of the following operations:
• the oxidation operation (E2a) can for example be carried out by heating the structure to a temperature between 800°C and 1100°C for a few minutes to a few hours under an oxidizing atmosphere, for example water vapor (oxidation wet) or oxygen alone (dry oxidation). During this oxidation, the two faces of the first SOI oxidize.
• the deoxidation operation (E2b) can for example be carried out by exposing the front face of the structure to a solution of hydrofluoric acid (HF) for a few seconds to a few minutes to remove the oxide layer formed on the front face, without removing the oxide layer present on the rear face of the structure.
• HF hydrofluoric acid
• This oxidation/deoxidation step consumes, by oxidation then elimination, a surface portion of silicon.
• the consumption of superficial silicon makes it possible not only to adjust the thickness of the semi-conductor layer but also to eliminate defects which appear following layer transfer by Smart CutTM, on the surface of the transferred layer.
• Long-term thermal annealing known as “batch annealing”, corresponds to thermal annealing lasting on the order of a few minutes to a few hours, generally greater than 15 min, advantageously carried out in a controlled-atmosphere furnace. The use of the oven makes it possible to treat a plurality of substrates at the same time.
• Thermal annealing is carried out at a temperature between 1 O ⁇ O'O and 1250°C for a few minutes to a few hours under an inert atmosphere, for example under an atmosphere of Argon or pure hydrogen or as a mixture.
• the surface treatment method in accordance with the invention finally comprises a final step (E4) of mechanical-chemical polishing.
• CMP chemical-mechanical polishing
• the surface to be polished is modified using a chemical agent, for example a suspension of silica particles. colloidal in a liquid base, and the modified surface is removed by mechanical abrasion.
• the speed of rotation and the pressure used during step (E4) of CMP are optimized so as to uniformly remove material from the surface of the transferred semiconductor layer or of the second electrically insulating layer, without however degrade the state of said surface, in particular without increasing its roughness.
• This mechanical-chemical polishing makes it possible to remove the surface particles. Furthermore, insofar as this polishing is carried out up to the edge of the substrate, it also makes it possible to gradually reduce the irregularities in the thickness of the first SOI up to the edge of the wafer at the level of the crown of the first SOI, which allows a second gluing closer to the plate edge. Thus, the width of the crown resulting from the second transfer is reduced by Smart Cut TM .
• rapid thermal annealing is carried out at a temperature of between 1100°C and 1250 ⁇ 0 for a few seconds to a hundred seconds, for example under an atmosphere comprising argon or hydrogen, alone or in a mixture.
• the second structure of semiconductor-on-insulator type or upper SOI structure is formed on the lower SOI structure by a second transfer of a second single-crystal semiconductor layer 3b from a second donor substrate, on the front face of the first semiconductor-on-insulator type structure, a second electrically insulating layer 3a being at the interface between the first transferred semiconductor layer and the second donor substrate.
• the second donor substrate is a monocrystalline semiconductor substrate, for example a monocrystalline silicon substrate.
• the second donor substrate is in the form of a circular plate generally of the same diameter as the support substrate.
• the second layer transfer is made according to a second Smart CutTM process comprising:
• a second electrically insulating layer 3a being at the interface between the front face of the semiconductor-on-insulator type structure and the first donor substrate
• the embrittlement zone within the second donor substrate can be created by co-implantation of helium atoms and hydrogen atoms in the second donor substrate of the second semiconductor layer.
• the embrittlement zone is created by implanting hydrogen atoms.
• the second layer transfer can be carried out by thinning the second donor substrate by its face opposite to the face bonded to the second electrically insulating layer until the desired thickness is obtained for the second semiconductor layer 3b.
• the second electrically insulating layer 3a is formed on the second donor substrate, so that, during the transfer of the second semiconductor layer 3b, said second electrically insulating layer 3a is also transferred and is interposed between the first semiconductor layer 2b and said second semiconductor layer 3b.
• the second electrically insulating layer 3a is prepared for example by oxidation of the second donor substrate, so that if the second donor substrate is a silicon substrate, the second electrically insulating layer 3a is a layer of silicon oxide.
• the second electrically insulating layer 3a is preferentially formed on the second donor substrate prior to the formation of the embrittlement zone within the second donor substrate by implantation of atoms through the second electrically insulating layer 3a.
• the second electrically insulating layer 3a is formed on the first semiconductor layer 2b so that, during the transfer of the second semiconductor layer 3b, said second electrically insulating layer 3a is inserted between the first semiconductor layer 2b and the second semiconductor layer 3b.
• the second electrically insulating layer 3a is for example prepared by oxidation of the front face of the first transferred semiconductor layer 2b, so that if the first donor substrate is a silicon substrate, the second electrically insulating layer 3a is a layer of silicon oxide. Said additional step of forming the second electrically insulating layer 3a is implemented after the treatment of the free surface of the first semiconductor layer 2b.
• the steps (E1), (E2) and (E3) of said method are implemented on the free surface of the first transferred semiconductor layer 2b before the step of forming the second electrically insulating layer 3a and the step (E4) can be implemented before and after said step of forming the second electrically insulating layer 3a, respectively on the surface of the first transferred semiconductor layer 2b and on the surface of the second electrically insulating layer 3a.
• the implementation of the surface treatment method in accordance with the invention which notably combines thermal smoothing and a CMP step, coupled with the use of an "ultra-flat" support substrate, allows to obtain an SOI structure which has a very small or even zero quantity of holes and a double crown width of less than 3 mm.
• These treatments are known to those skilled in the art and include, for example, rapid thermal annealing.

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• 2022
  • 2022-01-31 FR FR2200849A patent/FR3132380B1/fr active Active
• 2023
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  • 2023-01-30 EP EP23706412.6A patent/EP4473560A1/fr active Pending
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  • 2023-01-30 JP JP2024543908A patent/JP2025504525A/ja active Pending
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