CN118633150A - 用于制造双绝缘体上半导体结构的方法 - Google Patents

用于制造双绝缘体上半导体结构的方法 Download PDF

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Publication number
CN118633150A
CN118633150A CN202380019046.5A CN202380019046A CN118633150A CN 118633150 A CN118633150 A CN 118633150A CN 202380019046 A CN202380019046 A CN 202380019046A CN 118633150 A CN118633150 A CN 118633150A
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CN
China
Prior art keywords
semiconductor layer
donor substrate
substrate
electrically insulating
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202380019046.5A
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English (en)
Chinese (zh)
Inventor
卡里纳·杜雷特
卢多维克·埃卡尔诺
C·波特
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN118633150A publication Critical patent/CN118633150A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/64—Wet etching of semiconductor materials
    • H10P50/642—Chemical etching
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials

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  • Element Separation (AREA)
CN202380019046.5A 2022-01-31 2023-01-30 用于制造双绝缘体上半导体结构的方法 Pending CN118633150A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FRFR2200849 2022-01-31
FR2200849A FR3132380B1 (fr) 2022-01-31 2022-01-31 Procédé de fabrication d’une structure de type double semi-conducteur sur isolant
PCT/FR2023/050116 WO2023144496A1 (fr) 2022-01-31 2023-01-30 Procédé de fabrication d'une structure de type double semi-conducteur sur isolant

Publications (1)

Publication Number Publication Date
CN118633150A true CN118633150A (zh) 2024-09-10

Family

ID=81449054

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202380019046.5A Pending CN118633150A (zh) 2022-01-31 2023-01-30 用于制造双绝缘体上半导体结构的方法

Country Status (8)

Country Link
US (1) US20250140601A1 (https=)
EP (1) EP4473560A1 (https=)
JP (1) JP2025504525A (https=)
KR (1) KR20240142524A (https=)
CN (1) CN118633150A (https=)
FR (1) FR3132380B1 (https=)
TW (1) TW202347607A (https=)
WO (1) WO2023144496A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117594522A (zh) * 2023-12-25 2024-02-23 中国科学院微电子研究所 一种新型绝缘体上硅晶圆及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3975634B2 (ja) * 2000-01-25 2007-09-12 信越半導体株式会社 半導体ウェハの製作法
US7160753B2 (en) * 2004-03-16 2007-01-09 Voxtel, Inc. Silicon-on-insulator active pixel sensors
JP5673572B2 (ja) * 2012-01-24 2015-02-18 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
FR2987935B1 (fr) * 2012-03-12 2016-07-22 Soitec Silicon On Insulator Procede d'amincissement de la couche active de silicium d'un substrat du type "silicium sur isolant" (soi).

Also Published As

Publication number Publication date
FR3132380B1 (fr) 2024-11-29
US20250140601A1 (en) 2025-05-01
WO2023144496A1 (fr) 2023-08-03
JP2025504525A (ja) 2025-02-12
EP4473560A1 (fr) 2024-12-11
TW202347607A (zh) 2023-12-01
KR20240142524A (ko) 2024-09-30
FR3132380A1 (fr) 2023-08-04

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