FR3132380B1 - Procédé de fabrication d’une structure de type double semi-conducteur sur isolant - Google Patents
Procédé de fabrication d’une structure de type double semi-conducteur sur isolant Download PDFInfo
- Publication number
- FR3132380B1 FR3132380B1 FR2200849A FR2200849A FR3132380B1 FR 3132380 B1 FR3132380 B1 FR 3132380B1 FR 2200849 A FR2200849 A FR 2200849A FR 2200849 A FR2200849 A FR 2200849A FR 3132380 B1 FR3132380 B1 FR 3132380B1
- Authority
- FR
- France
- Prior art keywords
- donor substrate
- transferred
- manufacturing
- semiconductor
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/90—Thermal treatments, e.g. annealing or sintering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/60—Wet etching
- H10P50/64—Wet etching of semiconductor materials
- H10P50/642—Chemical etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P52/40—Chemomechanical polishing [CMP]
- H10P52/402—Chemomechanical polishing [CMP] of semiconductor materials
Landscapes
- Element Separation (AREA)
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2200849A FR3132380B1 (fr) | 2022-01-31 | 2022-01-31 | Procédé de fabrication d’une structure de type double semi-conducteur sur isolant |
| CN202380019046.5A CN118633150A (zh) | 2022-01-31 | 2023-01-30 | 用于制造双绝缘体上半导体结构的方法 |
| EP23706412.6A EP4473560A1 (fr) | 2022-01-31 | 2023-01-30 | Procédé de fabrication d'une structure de type double semi-conducteur sur isolant |
| PCT/FR2023/050116 WO2023144496A1 (fr) | 2022-01-31 | 2023-01-30 | Procédé de fabrication d'une structure de type double semi-conducteur sur isolant |
| KR1020247029136A KR20240142524A (ko) | 2022-01-31 | 2023-01-30 | 이중 반도체-온-절연체 구조물을 제조하기 위한 공정 |
| TW112103175A TW202347607A (zh) | 2022-01-31 | 2023-01-30 | 用於製作雙重絕緣體上半導體結構之方法 |
| JP2024543908A JP2025504525A (ja) | 2022-01-31 | 2023-01-30 | 二重半導体オンインシュレータ構造を作製するためのプロセス |
| US18/834,746 US20250140601A1 (en) | 2022-01-31 | 2023-01-30 | Process for fabricating a double semiconductor-on-insulator structure |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2200849A FR3132380B1 (fr) | 2022-01-31 | 2022-01-31 | Procédé de fabrication d’une structure de type double semi-conducteur sur isolant |
| FR2200849 | 2022-01-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR3132380A1 FR3132380A1 (fr) | 2023-08-04 |
| FR3132380B1 true FR3132380B1 (fr) | 2024-11-29 |
Family
ID=81449054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR2200849A Active FR3132380B1 (fr) | 2022-01-31 | 2022-01-31 | Procédé de fabrication d’une structure de type double semi-conducteur sur isolant |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US20250140601A1 (https=) |
| EP (1) | EP4473560A1 (https=) |
| JP (1) | JP2025504525A (https=) |
| KR (1) | KR20240142524A (https=) |
| CN (1) | CN118633150A (https=) |
| FR (1) | FR3132380B1 (https=) |
| TW (1) | TW202347607A (https=) |
| WO (1) | WO2023144496A1 (https=) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117594522A (zh) * | 2023-12-25 | 2024-02-23 | 中国科学院微电子研究所 | 一种新型绝缘体上硅晶圆及其制备方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3975634B2 (ja) * | 2000-01-25 | 2007-09-12 | 信越半導体株式会社 | 半導体ウェハの製作法 |
| US7160753B2 (en) * | 2004-03-16 | 2007-01-09 | Voxtel, Inc. | Silicon-on-insulator active pixel sensors |
| JP5673572B2 (ja) * | 2012-01-24 | 2015-02-18 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
| FR2987935B1 (fr) * | 2012-03-12 | 2016-07-22 | Soitec Silicon On Insulator | Procede d'amincissement de la couche active de silicium d'un substrat du type "silicium sur isolant" (soi). |
-
2022
- 2022-01-31 FR FR2200849A patent/FR3132380B1/fr active Active
-
2023
- 2023-01-30 WO PCT/FR2023/050116 patent/WO2023144496A1/fr not_active Ceased
- 2023-01-30 EP EP23706412.6A patent/EP4473560A1/fr active Pending
- 2023-01-30 KR KR1020247029136A patent/KR20240142524A/ko active Pending
- 2023-01-30 JP JP2024543908A patent/JP2025504525A/ja active Pending
- 2023-01-30 US US18/834,746 patent/US20250140601A1/en active Pending
- 2023-01-30 TW TW112103175A patent/TW202347607A/zh unknown
- 2023-01-30 CN CN202380019046.5A patent/CN118633150A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20250140601A1 (en) | 2025-05-01 |
| WO2023144496A1 (fr) | 2023-08-03 |
| JP2025504525A (ja) | 2025-02-12 |
| EP4473560A1 (fr) | 2024-12-11 |
| CN118633150A (zh) | 2024-09-10 |
| TW202347607A (zh) | 2023-12-01 |
| KR20240142524A (ko) | 2024-09-30 |
| FR3132380A1 (fr) | 2023-08-04 |
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Legal Events
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|---|---|---|---|
| PLFP | Fee payment |
Year of fee payment: 2 |
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| PLSC | Publication of the preliminary search report |
Effective date: 20230804 |
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| PLFP | Fee payment |
Year of fee payment: 3 |
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| PLFP | Fee payment |
Year of fee payment: 4 |
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| PLFP | Fee payment |
Year of fee payment: 5 |