JP2023024670A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2023024670A JP2023024670A JP2022205642A JP2022205642A JP2023024670A JP 2023024670 A JP2023024670 A JP 2023024670A JP 2022205642 A JP2022205642 A JP 2022205642A JP 2022205642 A JP2022205642 A JP 2022205642A JP 2023024670 A JP2023024670 A JP 2023024670A
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- circuit pattern
- semiconductor chips
- external terminal
- arm portion
- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 192
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- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 10
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/538—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a push-pull configuration
Abstract
Description
以下、図面を参照して、第1の実施の形態の半導体装置に含まれるアーム部について、図1を用いて説明する。図1は、第1の実施の形態の半導体装置に含まれるアーム部を説明するための図である。第1の実施の形態の半導体装置1は、図1に示す、アーム部2を備えている。アーム部2は、積層基板3と積層基板3上に配置された第1半導体チップ6,7とを有している。第1半導体チップ6,7は、裏面に第1正極電極(図示を省略)を、おもて面に第1負極電極6b,7b及び第1制御電極6a,7aをそれぞれ備える。このような第1半導体チップ6,7は、例えば、パワーMOSFET、または、RC(Reverse-Conducting)-IGBTを適用することができる。RC-IGBTは、IGBTとFWDが1チップ内に含まれたものである。
第2の実施の形態では、第1の実施の形態の半導体装置についてより具体的に説明する。まず、半導体装置について図2及び図3を用いて説明する。図2は、第2の実施の形態の半導体装置の平面図であり、図3は、第2の実施の形態の半導体装置の断面図である。なお、図3(A)は、図2における一点鎖線X1-X1の、図3(B)は、図2における一点鎖線X2-X2のそれぞれの断面図である。
2 アーム部
3 積層基板
4 基板
5a 第1回路パターン
5a1 第1配置領域
5b 第2回路パターン
6,7 第1半導体チップ
6a,7a 第1制御電極
6b,7b 第1負極電極
8a~8e 配線部材
20 第1アーム部
21,31 セラミック回路基板
22,32 絶縁板
23a~23d,33a~33e 回路パターン
23a1 第1配置領域
33a1 第2配置領域
24,34 金属板
25,26,35,36 半導体チップ
25a,26a,35a,36a ゲート電極
25b,26b,35b,36b エミッタ電極
27a~27j,37a~37i ボンディングワイヤ
30 第2アーム部
40 ケース
41 筐体
42 収納領域
43~45 外部端子部
Claims (3)
- 第1外部端子部と、
前記第1外部端子部に接続された第1アーム部と、
を備え、
前記第1アーム部は、
平面視で凹形状を成す第1回路パターンと、
平面視で前記第1回路パターンの窪みからなる第1配置領域に少なくとも一部が配置された第2回路パターンと、
裏面に第1電極を、おもて面に、第1制御電極及び第1配線部材により前記第2回路パターンと電気的に接続される第2電極をそれぞれ備え、前記第1配置領域を挟んで前記第1回路パターンにそれぞれの前記第1電極が配置される第1半導体チップと、
前記窪みの開口方向とは反対側の前記第1半導体チップから離れる方向に延伸し、前記第1回路パターンと前記第1外部端子部とを電気的に接続する配線部材と、
を備える、
半導体装置。 - 前記配線部材の一端は、前記第1回路パターンの前記第1配置領域に対向し電気的に前記第1半導体チップ間の領域に接続している、
請求項1に記載の半導体装置。 - 第1外部端子部と、
第2外部端子部と、
第3外部端子部と、
前記第1外部端子部および前記第3外部端子部に接続された第1アーム部と、
前記第1外部端子部および前記第2外部端子部に接続された第2アーム部と、
を有し、
前記第1アーム部は、
平面視で凹形状を成す第1回路パターンと、
平面視で前記第1回路パターンの窪みからなる第1配置領域に少なくとも一部が配置された第2回路パターンと、
裏面に第1電極を、おもて面に、第1制御電極及び第1配線部材により前記第2回路パターンと電気的に接続される第2電極をそれぞれ備え、前記第1配置領域を挟んで前記第1回路パターンにそれぞれの前記第1電極が配置される第1半導体チップと、
前記窪みの開口方向とは反対側の前記第1半導体チップから離れる方向に延伸し、前記第1回路パターンと前記第1外部端子部とを電気的に接続する配線部材と、
を備え、
前記第2アーム部は、
平面視で凹形状を成す第3回路パターンと、
平面視で前記第3回路パターンの前記窪みからなる第2配置領域に少なくとも一部が配置された第4回路パターンと、
裏面に第3電極を、おもて面に、第2制御電極及び第2配線部材により前記第4回路パターンに電気的に接続される第4電極をそれぞれ備え、前記第2配置領域を挟んで前記第3回路パターンにそれぞれの前記第3電極が配置される第2半導体チップと、
を備え、
さらに、前記第1回路パターンと前記第4回路パターンとを接続する配線部材を備え、
前記第3回路パターンは、前記第2外部端子部と電気的に接続しており、
前記第2回路パターンは、前記第3外部端子部と電気的に接続している半導体装置。
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