JP2021515983A - 回路ダイと相互接続部との間の自動位置合わせ - Google Patents

回路ダイと相互接続部との間の自動位置合わせ Download PDF

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Publication number
JP2021515983A
JP2021515983A JP2020546450A JP2020546450A JP2021515983A JP 2021515983 A JP2021515983 A JP 2021515983A JP 2020546450 A JP2020546450 A JP 2020546450A JP 2020546450 A JP2020546450 A JP 2020546450A JP 2021515983 A JP2021515983 A JP 2021515983A
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JP
Japan
Prior art keywords
channel
circuit die
pocket
channels
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2020546450A
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English (en)
Japanese (ja)
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JPWO2019171214A5 (https=
JP2021515983A5 (https=
Inventor
マハジャン，アンキット
エル． ペクロフスキー，ミカイル
エル． ペクロフスキー，ミカイル
エー． シャー，セーガー
エー． シャー，セーガー
ジェイ． メッツラー，トーマス
ジェイ． メッツラー，トーマス
エー． メイヤー，カラ
エー． メイヤー，カラ
ジュ，ジェームズ
エム． ゲデール，テレサ
エム． ゲデール，テレサ
エー． ペクロフスキー，リュドミラ
エー． ペクロフスキー，リュドミラ
ダブリュ． ケムリング，ジョナサン
ダブリュ． ケムリング，ジョナサン
ケー． ラーセン，ジェレミー
ケー． ラーセン，ジェレミー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
3M Innovative Properties Co
Original Assignee
3M Innovative Properties Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Co filed Critical 3M Innovative Properties Co
Publication of JP2021515983A publication Critical patent/JP2021515983A/ja
Publication of JPWO2019171214A5 publication Critical patent/JPWO2019171214A5/ja
Publication of JP2021515983A5 publication Critical patent/JP2021515983A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/01—Manufacture or treatment
    • H10W76/05—Providing fillings in containers, e.g. gas filling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/688—Flexible insulating substrates

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
JP2020546450A 2018-03-06 2019-02-27 回路ダイと相互接続部との間の自動位置合わせ Pending JP2021515983A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862639234P 2018-03-06 2018-03-06
US62/639,234 2018-03-06
PCT/IB2019/051585 WO2019171214A1 (en) 2018-03-06 2019-02-27 Automatic registration between circuit dies and interconnects

Publications (3)

Publication Number Publication Date
JP2021515983A true JP2021515983A (ja) 2021-06-24
JPWO2019171214A5 JPWO2019171214A5 (https=) 2022-03-10
JP2021515983A5 JP2021515983A5 (https=) 2022-03-10

Family

ID=67846934

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020546450A Pending JP2021515983A (ja) 2018-03-06 2019-02-27 回路ダイと相互接続部との間の自動位置合わせ

Country Status (6)

Country Link
US (1) US20210035875A1 (https=)
EP (1) EP3762965A1 (https=)
JP (1) JP2021515983A (https=)
CN (1) CN111819686A (https=)
TW (1) TW201943010A (https=)
WO (1) WO2019171214A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020058815A1 (en) 2018-09-17 2020-03-26 3M Innovative Properties Company Flexible device including conductive traces with enhanced stretchability
EP3906759A4 (en) 2018-12-31 2022-10-12 3M Innovative Properties Company Flexible circuits on soft substrates
US11937381B2 (en) 2018-12-31 2024-03-19 3M Innovative Properties Company Forming electrical interconnections using capillary microfluidics
US12020951B2 (en) 2019-04-29 2024-06-25 3M Innovative Properties Company Methods for registration of circuit dies and electrical interconnects
CN114746988A (zh) 2019-12-04 2022-07-12 3M创新有限公司 包括微图案并使用部分固化以粘附管芯的电路
EP4094289A1 (en) 2020-01-24 2022-11-30 3M Innovative Properties Company Electrical connections to embedded electronic components

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350233A (ja) * 1993-06-10 1994-12-22 Sankyo Seiki Mfg Co Ltd 回路基板
JP2006332615A (ja) * 2005-04-25 2006-12-07 Brother Ind Ltd パターン形成方法
JP2008211150A (ja) * 2007-02-28 2008-09-11 Seiko Instruments Inc ３次元構造体部品、及びその製造方法
JP2010533939A (ja) * 2007-07-19 2010-10-28 バイエル・マテリアルサイエンス・アクチェンゲゼルシャフト 微細伝導性構造体を表面に製造する方法
JP2011249357A (ja) * 2010-05-21 2011-12-08 Panasonic Electric Works Co Ltd 回路基板および回路基板の製造方法
US20140141156A1 (en) * 2012-11-22 2014-05-22 Samsung Electronics Co., Ltd. Method of forming electric wiring using inkjet printing
JP2017147269A (ja) * 2016-02-15 2017-08-24 株式会社デンソー 車両用電装部品の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5454161A (en) * 1993-04-29 1995-10-03 Fujitsu Limited Through hole interconnect substrate fabrication process
WO2006100790A1 (ja) * 2005-03-22 2006-09-28 Cluster Technology Co., Ltd. 配線基板の製造方法及び配線基板
CN102157510B (zh) * 2010-02-12 2013-11-06 亿光电子工业股份有限公司 近接传感器封装结构及其制作方法
CN103190204B (zh) * 2010-11-03 2016-11-16 3M创新有限公司 具有无引线接合管芯的柔性led器件

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06350233A (ja) * 1993-06-10 1994-12-22 Sankyo Seiki Mfg Co Ltd 回路基板
JP2006332615A (ja) * 2005-04-25 2006-12-07 Brother Ind Ltd パターン形成方法
JP2008211150A (ja) * 2007-02-28 2008-09-11 Seiko Instruments Inc ３次元構造体部品、及びその製造方法
JP2010533939A (ja) * 2007-07-19 2010-10-28 バイエル・マテリアルサイエンス・アクチェンゲゼルシャフト 微細伝導性構造体を表面に製造する方法
JP2011249357A (ja) * 2010-05-21 2011-12-08 Panasonic Electric Works Co Ltd 回路基板および回路基板の製造方法
US20140141156A1 (en) * 2012-11-22 2014-05-22 Samsung Electronics Co., Ltd. Method of forming electric wiring using inkjet printing
JP2017147269A (ja) * 2016-02-15 2017-08-24 株式会社デンソー 車両用電装部品の製造方法

Also Published As

Publication number Publication date
EP3762965A1 (en) 2021-01-13
CN111819686A (zh) 2020-10-23
WO2019171214A1 (en) 2019-09-12
US20210035875A1 (en) 2021-02-04
TW201943010A (zh) 2019-11-01

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