JP2021515983A - 回路ダイと相互接続部との間の自動位置合わせ - Google Patents
回路ダイと相互接続部との間の自動位置合わせ Download PDFInfo
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- 239000007788 liquid Substances 0.000 claims abstract description 114
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 239000007787 solid Substances 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims description 13
- 239000002861 polymer material Substances 0.000 claims description 6
- 239000012530 fluid Substances 0.000 abstract description 18
- 239000000853 adhesive Substances 0.000 description 28
- 230000001070 adhesive effect Effects 0.000 description 28
- 239000000976 ink Substances 0.000 description 13
- 239000008393 encapsulating agent Substances 0.000 description 9
- 239000010410 layer Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 238000004891 communication Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 230000007935 neutral effect Effects 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000007711 solidification Methods 0.000 description 4
- 230000008023 solidification Effects 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000012776 electronic material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 229910001338 liquidmetal Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000520 microinjection Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- -1 polyethylene terephthalate Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000011343 solid material Substances 0.000 description 2
- 238000010146 3D printing Methods 0.000 description 1
- 229920001342 Bakelite® Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000004676 acrylonitrile butadiene styrene Substances 0.000 description 1
- 229920006125 amorphous polymer Polymers 0.000 description 1
- 239000004637 bakelite Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000004049 embossing Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 238000007646 gravure printing Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005499 meniscus Effects 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 238000002174 soft lithography Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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Abstract
Description
ある特定の用語が、本明細書及び特許請求の範囲の全体を通して使用されており、これらの大部分については周知であるが、何らかの説明が必要とされる場合もある。以下を理解されたい:
用語「導電性液体」は、毛管現象によってチャネル内を流動可能な液体組成物を指す。本明細書中に記載される導電性液体は、固化させて、導電性トレースを形成することができる。導電性液体は、導電性トレースの形成に使用するのに望ましい性質を有する任意の適切な電子材料を含んでもよい。
実施形態1〜10及び11〜23はいずれも組み合わせることができることを理解されたい。
主表面を有する基板と、
基板の主表面の位置合わせ領域上に配置された固体回路ダイであって、その底面上に、1つ以上の接触パッドを有する固体回路ダイと、
基板の主表面上に配置され、位置合わせ領域内に延び、固体回路ダイの底面の下にある部分を有する、1つ以上のチャネルと、
1つ以上のチャネル内に形成された1つ以上の導電性トレースであって、導電性トレースは固体回路ダイの接触パッドと直接接触している、1つ以上の導電性トレースと、
を備える、物品。
主表面を有する基板を用意することと、
基板の主表面の位置合わせ領域上に固体回路ダイを配置することであって、固体回路ダイはその底面上に、1つ以上の接触パッドを有する、ことと、
基板の主表面上に1つ以上のチャネルを形成することであって、チャネルは、位置合わせ領域内に延び、固体回路ダイの底面の下にある部分を有する、ことと、
導電性液体をチャネル内に配置することと、
導電性液体を、固体回路ダイの底面上の接触パッドと直接接触させるために、主に毛細管圧によってチャネル内で流すことと、
導電性液体を硬化させて、固体回路ダイの接触パッドと直接接触する1つ以上の導電性トレースを形成することと、
を含む、方法。
Claims (20)
- 主表面を有する基板と、
前記基板の前記主表面の位置合わせ領域上に配置された固体回路ダイであって、その底面上に、1つ以上の接触パッドを有する固体回路ダイと、
前記基板の前記主表面上に配置されており、前記位置合わせ領域内に延び、前記固体回路ダイの前記底面の下にある部分を有する1つ以上のチャネルと、
前記1つ以上のチャネル内に形成された1つ以上の導電性トレースであって、前記固体回路ダイの前記接触パッドと直接接触している1つ以上の導電性トレースと、
を備える、物品。 - 前記チャネルは、入口チャネルと出口チャネルとを備え、前記入口チャネルと前記出口チャネルは、流体的に接続されて内部チャネルを形成し、前記内部チャネルの少なくとも一部分は、前記固体回路ダイの前記底面の下にある、請求項1に記載の物品。
- 前記基板は、前記チャネルの少なくとも1つに隣接して配置された1つ以上の安全チャネルを更に備える、請求項1に記載の物品。
- 前記安全チャネルの少なくとも1つは、前記固体回路ダイの底面の下にあるように延びている、請求項3に記載の物品。
- 前記位置合わせ領域は、前記固体回路ダイを受け入れるためのポケットを備える、請求項1に記載の物品。
- 前記ポケットは傾斜した側壁を含み、前記チャネルの少なくとも1つは前記傾斜した側壁を横切って延びている、請求項5に記載の物品。
- 前記ポケットは、前記ポケットの縁部と前記固体回路ダイとの間にギャップが存在するように大きさが拡大されており、前記ギャップは、要求される公差の少なくとも3倍超である、請求項5に記載の物品。
- 前記チャネルは、封入材料により埋め戻されている、請求項1に記載の物品。
- 前記基板は、不定長ポリマー材料のウェブを含むフレキシブル基板である、請求項1に記載の物品。
- 主表面を有する基板を提供することと、
前記基板の前記主表面の位置合わせ領域上に固体回路ダイを提供することであって、前記固体回路ダイは、その底面上に1つ以上の接触パッドを有する、固体回路ダイを提供することと、
前記基板の前記主表面上に1つ以上のチャネルを形成することであって、前記チャネルは、前記位置合わせ領域内に延び、前記固体回路ダイの前記底面の下にある部分を有する、チャネルを形成することと、
導電性液体を、前記固体回路ダイの前記底面上の前記接触パッドと直接接触させるために前記チャネル内に配置することと、
を含む方法。 - 前記導電性液体を配置することは、前記導電性液体を、主に毛細管圧によって前記チャネルに流すことを含む、請求項10に記載の方法。
- 前記導電性液体を、前記固体回路ダイの前記接触パッドと直接接触する1つ以上の導電性トレースを形成することを更に含む、請求項10に記載の方法。
- 前記チャネルは、流体的に接続された入口チャネルと出口チャネルとを備え、前記導電性液体は前記入口チャネルに流入する、請求項10に記載の方法。
- 前記導電性液体を前記入口チャネル内に配置することを更に含む、請求項13に記載の方法。
- 前記チャネルの少なくとも1つに隣接して配置され、前記隣接するチャネルからの導電性液体の流れを遮断するように構成された1つ以上の安全チャネルを提供することを更に含む、請求項10に記載の方法。
- 前記位置合わせ領域は、前記固体回路ダイを受け入れるためのポケットを含む、請求項10に記載の方法。
- 前記ポケットは傾斜した側壁を含み、前記チャネルの少なくとも1つは前記傾斜した側壁を横切って延びる、請求項16に記載の方法。
- 前記ポケットは、前記ポケットの縁部と前記固体回路ダイとの間にギャップが存在するように大きさが拡大されており、前記ギャップは、要求される公差の少なくとも3倍超である、請求項17に記載の方法。
- 前記チャネルを封入材料により埋め戻すことを更に含む、請求項10に記載の方法。
- ロールツーロール装置上で行われる、請求項10に記載の方法。
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US201862639234P | 2018-03-06 | 2018-03-06 | |
US62/639,234 | 2018-03-06 | ||
PCT/IB2019/051585 WO2019171214A1 (en) | 2018-03-06 | 2019-02-27 | Automatic registration between circuit dies and interconnects |
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EP (1) | EP3762965A1 (ja) |
JP (1) | JP2021515983A (ja) |
CN (1) | CN111819686A (ja) |
TW (1) | TW201943010A (ja) |
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WO2020058815A1 (en) | 2018-09-17 | 2020-03-26 | 3M Innovative Properties Company | Flexible device including conductive traces with enhanced stretchability |
US11937381B2 (en) | 2018-12-31 | 2024-03-19 | 3M Innovative Properties Company | Forming electrical interconnections using capillary microfluidics |
CN113228833A (zh) | 2018-12-31 | 2021-08-06 | 3M创新有限公司 | 软基板上的柔性电路 |
EP3963627A1 (en) | 2019-04-29 | 2022-03-09 | 3M Innovative Properties Company | Methods for registration of circuit dies and electrical interconnects |
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WO2012061182A1 (en) * | 2010-11-03 | 2012-05-10 | 3M Innovative Properties Company | Flexible led device with wire bond free die |
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- 2019-02-27 JP JP2020546450A patent/JP2021515983A/ja active Pending
- 2019-02-27 CN CN201980017362.2A patent/CN111819686A/zh not_active Withdrawn
- 2019-02-27 US US16/976,126 patent/US20210035875A1/en not_active Abandoned
- 2019-02-27 EP EP19763578.2A patent/EP3762965A1/en not_active Withdrawn
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US20210035875A1 (en) | 2021-02-04 |
CN111819686A (zh) | 2020-10-23 |
TW201943010A (zh) | 2019-11-01 |
EP3762965A1 (en) | 2021-01-13 |
WO2019171214A1 (en) | 2019-09-12 |
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