JP2020504439A - セミコンダクタオンインシュレータ基板の表面を平滑化するためのプロセス - Google Patents
セミコンダクタオンインシュレータ基板の表面を平滑化するためのプロセス Download PDFInfo
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- JP2020504439A JP2020504439A JP2019529245A JP2019529245A JP2020504439A JP 2020504439 A JP2020504439 A JP 2020504439A JP 2019529245 A JP2019529245 A JP 2019529245A JP 2019529245 A JP2019529245 A JP 2019529245A JP 2020504439 A JP2020504439 A JP 2020504439A
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- 239000000758 substrate Substances 0.000 title claims abstract description 92
- 238000009499 grossing Methods 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000012212 insulator Substances 0.000 title description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 230000001590 oxidative effect Effects 0.000 claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000011261 inert gas Substances 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 6
- 230000003746 surface roughness Effects 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000003313 weakening effect Effects 0.000 abstract description 5
- 230000032798 delamination Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 abstract 1
- 238000011282 treatment Methods 0.000 description 11
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 238000002513 implantation Methods 0.000 description 8
- 230000007935 neutral effect Effects 0.000 description 8
- 238000004151 rapid thermal annealing Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000005259 measurement Methods 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 238000004299 exfoliation Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000013626 chemical specie Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052756 noble gas Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004439 roughness measurement Methods 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 230000007847 structural defect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (11)
- a)内部に脆弱化ゾーンを有するドナー基板を用意するステップであって、前記脆弱化ゾーンが、前記ドナー基板の移動されるべき層と残余部との間に境界を形成する、ステップと、
b)前記ドナー基板をレシーバ基板に張り付けるステップであって、移動されるべき前記層が前記ドナー基板と前記レシーバ基板との間の界面に位置する、ステップと、
c)前記脆弱化ゾーンのところで、前記ドナー基板の前記残余部から、移動層とともに前記レシーバ基板を剥離するステップと、
を使用して、前記移動層を備える半導体基板を製造するためのプロセスにおいて、
前記プロセスが、剥離ステップc)の後で、前記移動層の表面に行われる平滑化の少なくとも1つのステップd)を含み、前記ステップd)ではステップc)から得られた前記半導体基板が、少なくとも剥離の瞬間から前記平滑化ステップの終わりまで、非酸化性不活性雰囲気中に又は非酸化性不活性ガスの混合物中に保たれることを特徴とする、プロセス。 - 前記剥離ステップ及び平滑化ステップが、非酸化性不活性雰囲気中で又は非酸化性不活性ガスの混合物中で、特に10ppmよりも低いO2のレベルで行われることを特徴とする、請求項1に記載のプロセス。
- 前記平滑化ステップが、前記剥離ステップの直後に行われることを特徴とする、請求項1又は2に記載のプロセス。
- 前記剥離ステップ及び前記平滑化ステップが、1つのそして同じ装置内で、特に1つのそして同じ炉内で行われることを特徴とする、請求項1〜3のいずれか一項に記載のプロセス。
- 前記平滑化ステップが、少なくとも1時間にわたり、好ましくは1〜3時間にわたり行われることを特徴とする、請求項1又は2に記載のプロセス。
- 前記剥離ステップが、熱処理を適用して、前記ドナー基板の前記残余部から前記脆弱化ゾーンのところで剥離を達成することにより行われることを特徴とする、請求項1〜5のいずれか一項に記載のプロセス。
- 前記平滑化ステップが、900℃よりも低い温度で、特に650℃〜900℃の温度範囲内で行われることを特徴とする、請求項1〜5のいずれか一項に記載のプロセス。
- 前記ドナー基板が、シリコン、単結晶シリコン、ゲルマニウム又はSiGeから選択されることを特徴とする、請求項1〜7のいずれか一項に記載のプロセス。
- 前記レシーバ基板が、シリコン、単結晶シリコン、そうでなければ700℃よりも高い温度に耐えるいずれかのタイプのベース基板から選択されることを特徴とする、請求項1〜8のいずれか一項に記載のプロセス。
- 前記移動層の二乗平均表面粗さが、0.1nmよりも小さく、特に前記平滑化ステップの後で0.3nmよりも小さく、そして特に表面全体にわたり小さいことを特徴とする、請求項1〜9のいずれか一項に記載のプロセス。
- 請求項1〜10のいずれか一項に記載のプロセスを使用して製造した半導体基板において、前記半導体基板が、移動層を含み、前記移動層の二乗平均表面粗さが、0.1nmより、特に0.3nmよりも小さく、そして特に表面全体にわたり小さいことを特徴とする、半導体基板。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1750300A FR3061988B1 (fr) | 2017-01-13 | 2017-01-13 | Procede de lissage de surface d'un substrat semiconducteur sur isolant |
FR1750300 | 2017-01-13 | ||
PCT/EP2018/050558 WO2018130568A1 (en) | 2017-01-13 | 2018-01-10 | Process for smoothing the surface of a semiconductor-on-insulator substrate |
Publications (2)
Publication Number | Publication Date |
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JP2020504439A true JP2020504439A (ja) | 2020-02-06 |
JP7159518B2 JP7159518B2 (ja) | 2022-10-25 |
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JP2019529245A Active JP7159518B2 (ja) | 2017-01-13 | 2018-01-10 | セミコンダクタオンインシュレータ基板の表面を平滑化するためのプロセス |
Country Status (6)
Country | Link |
---|---|
US (1) | US11276605B2 (ja) |
EP (1) | EP3568872B1 (ja) |
JP (1) | JP7159518B2 (ja) |
FR (1) | FR3061988B1 (ja) |
TW (1) | TWI683371B (ja) |
WO (1) | WO2018130568A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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FR3093715B1 (fr) | 2019-03-15 | 2021-03-05 | Soitec Silicon On Insulator | Dispositif de maintien pour un ensemble à fracturer |
FR3108440A1 (fr) | 2020-03-23 | 2021-09-24 | Soitec | Procédé de préparation d’une couche mince |
Citations (7)
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JP2000294754A (ja) * | 1999-04-07 | 2000-10-20 | Denso Corp | 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置 |
WO2005024925A1 (ja) * | 2003-09-05 | 2005-03-17 | Sumco Corporation | Soiウェーハの作製方法 |
JP2008182203A (ja) * | 2006-12-28 | 2008-08-07 | Covalent Materials Corp | シリコンウエハの熱処理方法 |
JP2011502358A (ja) * | 2007-10-31 | 2011-01-20 | コーニング インコーポレイテッド | 半導体・オン・インシュレータ装置を形成するための基板組成および方法の改善 |
JP2012231172A (ja) * | 2000-05-30 | 2012-11-22 | Commissariat A L'energie Atomique & Aux Energies Alternatives | 脆弱化された基板およびそのような基板の製造方法 |
JP2014120587A (ja) * | 2012-12-14 | 2014-06-30 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
JP2016516304A (ja) * | 2013-03-14 | 2016-06-02 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | ライトポイント欠陥と表面粗さを低減するための半導体オンインシュレータウエハの製造方法 |
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JP2002110949A (ja) * | 2000-09-28 | 2002-04-12 | Canon Inc | Soiの熱処理方法及び製造方法 |
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FR2912259B1 (fr) * | 2007-02-01 | 2009-06-05 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat du type "silicium sur isolant". |
US8163628B2 (en) * | 2007-11-01 | 2012-04-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate |
JP4919123B2 (ja) * | 2010-03-08 | 2012-04-18 | Tdk株式会社 | 処理基板収納ポッド及び処理基板収納ポッドの蓋開閉システム |
US8859393B2 (en) * | 2010-06-30 | 2014-10-14 | Sunedison Semiconductor Limited | Methods for in-situ passivation of silicon-on-insulator wafers |
FR3020175B1 (fr) * | 2014-04-16 | 2016-05-13 | Soitec Silicon On Insulator | Procede de transfert d'une couche utile |
WO2016109502A1 (en) * | 2014-12-31 | 2016-07-07 | Sunedison Semiconductor Limited | Preparation of silicon-germanium-on-insulator structures |
FR3032555B1 (fr) * | 2015-02-10 | 2018-01-19 | Soitec | Procede de report d'une couche utile |
US9831115B2 (en) * | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
-
2017
- 2017-01-13 FR FR1750300A patent/FR3061988B1/fr active Active
- 2017-12-13 TW TW106143704A patent/TWI683371B/zh active
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2018
- 2018-01-10 JP JP2019529245A patent/JP7159518B2/ja active Active
- 2018-01-10 US US16/473,475 patent/US11276605B2/en active Active
- 2018-01-10 WO PCT/EP2018/050558 patent/WO2018130568A1/en unknown
- 2018-01-10 EP EP18700158.1A patent/EP3568872B1/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2000294754A (ja) * | 1999-04-07 | 2000-10-20 | Denso Corp | 半導体基板及び半導体基板の製造方法並びに半導体基板製造装置 |
JP2012231172A (ja) * | 2000-05-30 | 2012-11-22 | Commissariat A L'energie Atomique & Aux Energies Alternatives | 脆弱化された基板およびそのような基板の製造方法 |
WO2005024925A1 (ja) * | 2003-09-05 | 2005-03-17 | Sumco Corporation | Soiウェーハの作製方法 |
JP2008182203A (ja) * | 2006-12-28 | 2008-08-07 | Covalent Materials Corp | シリコンウエハの熱処理方法 |
JP2011502358A (ja) * | 2007-10-31 | 2011-01-20 | コーニング インコーポレイテッド | 半導体・オン・インシュレータ装置を形成するための基板組成および方法の改善 |
JP2014120587A (ja) * | 2012-12-14 | 2014-06-30 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
JP2016516304A (ja) * | 2013-03-14 | 2016-06-02 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | ライトポイント欠陥と表面粗さを低減するための半導体オンインシュレータウエハの製造方法 |
Also Published As
Publication number | Publication date |
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TW201826402A (zh) | 2018-07-16 |
FR3061988A1 (fr) | 2018-07-20 |
FR3061988B1 (fr) | 2019-11-01 |
EP3568872B1 (en) | 2022-03-02 |
JP7159518B2 (ja) | 2022-10-25 |
WO2018130568A1 (en) | 2018-07-19 |
US20190348319A1 (en) | 2019-11-14 |
US11276605B2 (en) | 2022-03-15 |
EP3568872A1 (en) | 2019-11-20 |
TWI683371B (zh) | 2020-01-21 |
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